davis@clocs.cs.unc.edu (Mark Davis) (11/23/88)
Recently on comp.arch there has been discussion of a zero instruction
set computer (ZISC) which actually is a one operation computer. One
architecture is the Subtract and branch on less that zero instruction
with 3 or 4 operands (I find some references to Van der Poel, 1956
for this construction).
Has anyone ever tried to write a compiler for such a machine or done
any significant simulations?
Thanks - Mark
[I've heard that in the 1950's there was a Ph.D. thesis implementing a
Fortran compiler for a Turing machine, which is sort of the same spirit.
but would be fascinated to hear of any other work in that vein. I suspect
it would be filed under theory of computation. -John]
[From davis@clocs.cs.unc.edu (Mark Davis)]
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mail accidentally sent back to compilers. Meta-mail to ima!compilers-requestgert@prls.UUCP (Gert Slavenburg) (11/30/88)
Actually, I own a REAL HARDWARE OISC according to van der Poel. It runs
(crawls would be a better word) the PL0 high level language (a Pascal subset).
Its origin is immaterial, suffice it to say that some very bright and very
fanatic people put the hardware together in 1987 in the Netherlands, just for
fun, and decided to show that it could do everything that a computer was
supposed to do, by writing an interpreter for the PL0 virtual machine [Wirth
1976] for the 'van der Poel' instruction set. I am the 'caretaker' of the
machine.
The actual machine is a single board, designed to operate at a reasonably high
clock speed (I believe 12 MHz), using fast static RAM as main memory. The only
I/O of the 'computer' is a double UART, to hook it between an Atari/ST and a
terminal. The ST does the translation of the Pascal subset (PL0 from Wirth's
book 'Algorithms + Data Structures = Programs') to the PL0 virtual machine
code. There is no reason why the compiler couldn't be made to run on the OISC,
other than the fact that the current OISC board has a limited amount of
main memory and lacks file I/O devices (besides the obvious SPEED problem).
The whole thing was a fun exercise, but the actual machine runs and does its
job, hence showing once and for all that 'van der Poel' was right (of course).
However, don't think of this as the ultimate RISC. RISC is a carefull balance
of what to do in hardware and what to do in software - not a minimization of
the opcode set. The van der Poel machine is VERY SLOW on any task, given its
memory bandwidth, due to the fact that doing any computation at all requires
just too many instructions.
just thought I'd mention that it CAN and HAS BEEN done,
Gert Slavenburg
(UUCP : ..!pyramid!prls!gert)
[Wirth 1976] N. Wirth, 'Algorithms + Data Structures = Programs', Prentice Hall
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Send compilers articles to ima!compilers or, in a pinch, to Levine@YALE.EDU
Plausible paths are { decvax | harvard | yale | bbn}!ima
Please send responses to the originator of the message -- I cannot forward
mail accidentally sent back to compilers. Meta-mail to ima!compilers-requestgert@prls.UUCP (Gert Slavenburg) (11/30/88)
Actually, I own a REAL HARDWARE OISC according to van der Poel. It runs (crawls would be a better word) the PL0 high level language (a Pascal subset). Its origin is immaterial, suffice it to say that some very bright and very fanatic people put the hardware together in 1987 in the Netherlands, just for fun, and decided to show that it could do everything that a computer was supposed to do, by writing an interpreter for the PL0 virtual machine [Wirth 1976] for the 'van der Poel' instruction set. I am the 'caretaker' of the machine. The actual machine is a single board, designed to operate at a reasonably high clock speed (I believe 12 MHz), using fast static RAM as main memory. The only I/O of the 'computer' is a double UART, to hook it between an Atari/ST and a terminal. The ST does the translation of the Pascal subset (PL0 from Wirth's book 'Algorithms + Data Structures = Programs') to the PL0 virtual machine code. There is no reason why the compiler couldn't be made to run on the OISC, other than the fact that the current OISC board has a limited amount of main memory and lacks file I/O devices (besides the obvious SPEED problem). The whole thing was a fun exercise, but the actual machine runs and does its job, hence showing once and for all that 'van der Poel' was right (of course). However, don't think of this as the ultimate RISC. RISC is a carefull balance of what to do in hardware and what to do in software - not a minimization of the opcode set. The van der Poel machine is VERY SLOW on any task, given its memory bandwidth, due to the fact that doing any computation at all requires just too many instructions. just thought I'd mention that it CAN and HAS BEEN done, Gert Slavenburg (UUCP : ..!pyramid!prls!gert) [Wirth 1976] N. Wirth, 'Algorithms + Data Structures = Programs', Prentice Hall