[comp.arch] module size estimation

vaughan@puma.cad.mcc.com (Paul Vaughan) (02/28/91)

I'm interested in how designers go about estimating the sizes of
various components for the purposes of
floorplanning/partitioning/architectural decision making. I assume
that fairly accurate (if not completely precise) area/aspect ratio
figures are commonly estimated for certain well characterized modules
given parameters of the intended process.  Such modules include CLA
adders, ripple carry adders, NxM multiplexors, register sets, caches
(of any particular well-known sort), and even higher level modules
such as whole MMU's, FPU's, ALU's. Less well characterized modules
include random logic and state machines implemented in any of the
popular design styles.

I'm interested in any formula's, algorithms, or tools in common use,
both simple and complex.  Pointers to literature and even general
discussion of approaches for any design style would be appreciated.

For instance, I assume that for many designs using existing processes,
certain modules can be found in component libraries and thus the
figures are simply already known. Some modules are simply constructed
from library components so just looking up the parts and adding it all
together gives an accurate assessment. For other designs using new but
not radically different processes, certain figures are simply scaled.
Other approaches involve adding up component parts and adding in
wiring allowances.

Most of the literature I've seen so far has focussed on estimation as
part of an automatic synthesis or floorplanning process for random
logic implemented as standard cells and for DSP-oriented datapaths and
controllers.

--

 Paul Vaughan, MCC CAD Program | ARPA: vaughan@mcc.com | Phone: [512] 338-3639
 Box 200195, Austin, TX 78720  | UUCP: ...!cs.utexas.edu!milano!cadillac!vaughan
----------------------------------------------------------------------------------
I spent from $3 to $10 today to pay interest on the national debt.  How about you?
----------------------------------------------------------------------------------