mash@mips.COM (John Mashey) (04/04/89)
While hunting something else, I ran across a nice article "'SCRAM Cache'
in Sun-4/110 Beats Traditional Caches", SUNtechnology, Summer 1988, by Ed Kelly.
This explains the use of Static Column DRAMs in the 110, and reminded me of
an interesting question or two about memory systems in general,
as people are increasingly taking advantage of SC or page-mode DRAMs.
The general idea is that successive accesses to the same physical page
of memory within a memory board (or some unit of memory, anyway)
run not at typical DRAM speeds, but at (slow)-SRAM speeds.
For example, MIPS M/2000s use this to get more bandwidth, using page-mode
DRAMs, but with an SRAM cache as well. The 110 design avoided a cache.
With such methods, it would appear that performance increases as
you add more memory boards, because there are more "pages" that you
can access quickly. (This, of course, is hardly new, and has been especially
true for large systems with lots of I/O).
Can anybody from Sun say if this (performance increase) is true with the 110?
Also, I'm curious to know what variation there is from bottom to
top, especially for realistic programs? Does anybody out there have
several different sizes of 110 and some numbers?
I'd guess that there would be more of an effect with no cache, than
with one, but I don't have any data. If there are other SCRAM-cache-like
systems around (aren't some of the 386-boxen out there built this way?),
does anybody have this sort of data on them?
--
-john mashey DISCLAIMER: <generic disclaimer, I speak for me only, etc>
UUCP: {ames,decwrl,prls,pyramid}!mips!mash OR mash@mips.com
DDD: 408-991-0253 or 408-720-1700, x253
USPS: MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086