irf@kuling.UUCP (Bo Thide') (05/28/91)
It seems that there are more Snakes that HP are about to let loose soon. The following are excerpts from articles publishe in 'Unigram.X'. No. 334, May 20-24, 1991: "Not content to rest on its laurels, Hewlett-Packard is said to be readying an entry-level, 25 MHz, Motorola-based workstation rated at 22 MIPS that'll come in under $5,000--and if that wasn't enough, the firm is also reported to be working on a low-end version of its recently launched Series 700 Snakes priced at under $10,000 and performing at 110 MIPS: it's dubbed the Bushwhacker, according to 'Electronic News'." No. 334, May 20-24, 1991: "... And Sources at Hewlett-Packard say the low-end version of its recently launched Series 700 Snake, tipped to do 110 MIPS at under $10,000, (UX No 334), is exceeding all expectations in the labs; it's presently codenamed Bushmaster -- not Bushwhacker as originally reported -- though the same sources say that they liked the name so much they'll be trying to get it adopted officially!" Bo --- ^ Bo Thide'-------------------------------------------------------------- |I| Swedish Institute of Space Physics, S-755 91 Uppsala, Sweden |R| Phone: (+46) 18-403000. Fax: (+46) 18-403100 /|F|\ INTERNET: bt@irfu.se UUCP: ...!uunet!mcvax!sunic!irfu!bt ~~U~~ -----------------------------------------------------------------sm5dfw
irf@kuling.UUCP (Bo Thide') (05/28/91)
In article <2070@kuling.UUCP> irf@kuling.DoCS.UU.SE (Bo Thide') writes: >The following are excerpts from articles publishe in 'Unigram.X'. ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^published >No. 334, May 20-24, 1991: ^^^^^335,^^^^^27-31 Sorry about the typos. Bo bt@irfu.se
gary@chpc.utexas.edu (Gary Smith) (05/29/91)
I'm interested in the sustainable memory bandpass between the D-cache and main memory on the Snake series. Anyone know what it is? Can it sustain two 64-bit operands each clock? If not, we have one more CPU that can sit and wait for memory, right? -- ---Gary Randolph Gary Smith Internet: gary@chpc.utexas.edu Systems Group Phonenet: (512) 471-2411 Center for High Performance Computing Snailnet: 10100 Burnet Road The University of Texas System Austin, Texas 78758-4497
mccalpin@perelandra.cms.udel.edu (John D. McCalpin) (05/29/91)
>>>>> On 28 May 91 19:17:46 GMT, gary@chpc.utexas.edu (Gary Smith) said:
Gary> I'm interested in the sustainable memory bandpass between the D-cache
Gary> and main memory on the Snake series. Anyone know what it is? Can it
Gary> sustain two 64-bit operands each clock? If not, we have one more CPU
Gary> that can sit and wait for memory, right?
Yes. The current HP9000/7x0 machines can effectively manage one
32-bit word per clock cycle from main memory to cache. I think they
do this as one 64-bit word every other cycle.
Since cache lines are 64 bytes long, and assuming an 8-cycle penalty
for a cache miss, we get an estimate of the sustainable bandwidth
between memory and D-cache of one 64-bit word every 4 clock cycles.
This can be compared to the rate of one 64-bit word every 2 cycles on
the IBM RS/6000-320 (the more expensive machines do a bit better).
Since the HP machines run at about twice the clock speed of the IBM
machines, one sees about the same absolute sustainable memory
bandwidth, and similar performance on bandwidth-limited computations.
--
John D. McCalpin mccalpin@perelandra.cms.udel.edu
Assistant Professor mccalpin@brahms.udel.edu
College of Marine Studies, U. Del. J.MCCALPIN/OMNETbdg@idaho.amdahl.com (Blaine Gaither) (05/30/91)
Any bets on which vendor will come out with the Mongoose system!
--
Blaine Gaither
Amdahl Corporation
143 No. 2nd East St., Rexburg, Idaho 83440-1619
UUCP:{ames,decwrl,sun,uunet}!amdahl!tetons!bdg (208) 356-8915
INTERNET: bdg@tetons.idaho.amdahl.com