glew@pdx007.intel.com (Andy Glew) (02/08/91)
A while back I posted tables comparing synchronization primitive
implementations on a number of processors to comp.arch. A number of
people requested the actual survey, and I asked them to wait until it
was a technical report.
Well, I finally finished my MS, "Synchronization Primitive
Implementation, including the Bus Abandonment Lock".
The first half, the survey, background information, is available as
the technical report CRHC91-7. Order info/address below.
(The second part, the trivial but original work, has not yet been made
into a report).
Sorry it took so long. Hope it helps someone.
By the way, I am moderately interested in periodically updating this
"Survey of Synchronization Primitives" to reflect changes in the state
of the practice. If you have information to add, please do (for
example, the R4000 stuff was only recently added, and probably is in
the TR, but not my MS).
Order info:
Report number: CRHC91-7
Report title: Frankly, I've forgotten, but it should be something like
"A Survey of Synchronization Primitive Implementations"
Address: Again, I am afraid that I do not have the "official"
address for publications, but hopefully these folks can help you:
Center for Reliable and High-performance Computing
Coordinated Sciences Laboratory
University of Illinois
1101 W. Springfield
Urbana, Illinois 61810
Mark it "attention: technical reports" or something similar.
NB: I am no longer at the University of Illinois, and I cannot mail you copies
myself. I don't have the source code online where I am now, so I cannot
email or ftp copies to you. You'll have to try and get it from the
University of Illinois.
--
Andy Glew, glew@mipon2.intel.com
Intel Corp., M/S JF1-19, 5200 NE Elam Young Parkway,
Hillsboro, Oregon 97124-6497long@crhc.uiuc.edu (Junsheng Long) (02/08/91)
In article <GLEW.91Feb7133013@pdx007.intel.com> glew@pdx007.intel.com (Andy Glew) writes: >Order info: > > Report number: CRHC91-7 > > Report title: Frankly, I've forgotten, but it should be something like > "A Survey of Synchronization Primitive Implementations" > > Address: Again, I am afraid that I do not have the "official" > address for publications, but hopefully these folks can help you: > > Center for Reliable and High-performance Computing > Coordinated Sciences Laboratory > University of Illinois > 1101 W. Springfield > Urbana, Illinois 61810 ^^^^^ Wrong zip code. It should be 61801. >Andy Glew, glew@mipon2.intel.com
glew@pdx007.intel.com (Andy Glew) (02/09/91)
Urghhh. Here's the previois posting with accurate order info:
A while back I posted tables comparing synchronization primitive
implementations on a number of processors to comp.arch. A number of
people requested the actual survey, and I asked them to wait until it
was a technical report.
Well, I finally finished my MS, "Synchronization Primitive
Implementation, including the Bus Abandonment Lock".
The first half, the survey, background information, is available as
the technical report CRHC91-7. Order info/address below.
(The second part, the trivial but original work, has not yet been made
into a report).
Sorry it took so long. Hope it helps someone.
By the way, I am moderately interested in periodically updating this
"Survey of Synchronization Primitives" to reflect changes in the state
of the practice. If you have information to add, please do (for
example, the R4000 stuff was only recently added, and probably is in
the TR, but not my MS).
Order info:
Report number: CRHC91-7
Report title: Frankly, I've forgotten, but it should be something like
"A Survey of Synchronization Primitive Implementations"
Address:
UIUC CRHC technical reports:
Carolin Rouse
5-111 CSL
Center for Reliable and High-performance Computing
Coordinated Sciences Laboratory
University of Illinois
1101 W. Springfield
Urbana, Illinois 61801
carolin@crhc.uiuc.edu
217-244-7171
NB: I am no longer at the University of Illinois, and I cannot mail you copies
myself. I don't have the source code online where I am now, so I cannot
email or ftp copies to you. You'll have to try and get it from the
University of Illinois.
--
Andy Glew, glew@mipon2.intel.com
Intel Corp., M/S JF1-19, 5200 NE Elam Young Parkway,
Hillsboro, Oregon 97124-6497
--
Andy Glew, glew@mipon2.intel.com
Intel Corp., M/S JF1-19, 5200 NE Elam Young Parkway,
Hillsboro, Oregon 97124-6497