bernhard@molly.tds.kth.se (Bernhard Stockman TDS) (03/23/89)
Thanks for all Your answers, here follows a summary:
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ISPS for UNIX
clemc@ccc.uu.uunet (Clem Cole):
The EE Dept at CMU also wrote a verion for UNIX in C. It not's quite
as complete as the original BLISS-10 version (which Dan Klien rewrote,
with some help from me, into compatible BLISS many-many-many years ago
- on VAX Serial #1 I might add) - which is the likely parent of the
version you are using now. The C version lacks the RTM stuff as I
recall, but the C version adds a bunch of other stuff. It has a
simulator and of course the compiler and the GDB stuff. One of the EE
students eventually wrote a system for his PhD that took an ISP like
substance in and spit out a layout for a chip [much simplificant
here]. I'm now a consultant and I have a copy of the C version circa two
years ago. I'll can act as an intemediary if you like, but you'll have to
cover my standard fees if I do. I had it running on Sun equipment when
I last tried it. It should run on BSD or System V without much sweat.
Mauricio.Breternitz@maxwell.ece.cmu.edu:
Contact Bruce Siegell (bss@sam.cs.cmu.edu); he did an UNIX tool to
compile ISPS.
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Architectures Work Bench (AWB)
hansm%duteca@????.nl (Hans Mulder, Univ. of Technology, Delft, Netherlands)
The AWB is a set of tools which allow evaluation of architecture features:
e.g. register sets, cache performance, instruction encoding, etc.
Most of the tools were developped by Chad Mitchel and by me, and are
currently actively extended and maintained by the AWB group at Stanford.
I do have the AWB (v 1.6) running, but unfortunately cannot provide you
with a copy; the AWB must be ordered via Mike Flynn. The AWB group
distributes an industry and a university version. Ask Flynn for details.
(flynn@mimd.stanford.edu)
(Henk Muller) henkm@uva.uucp
Reference:
Introductory User's Guide to the Architect's Workbench Tools,
J Torellas et al, Stanford University
Technical report CSL-TR-88-355
This article will contain some references to more detailed documentation.
josh@ibm.com (Joshua Knight)
Reference:
%T And Now a Case for More Complex Instruction Sets
%A Michael J. Flynn
%A Chad L. Mitchell
%A Johannes M. Mulder
%J IEEE Computer
%V 20
%N 9
%D September 1987
%P 71-83
%X Using a computer architecture simulation platform, we can perform
instruction set tradeoffs with a common optimizing compiler and workload.
jab@romeo.cs.duke.edu (John A. Board)
Architect's Workbench is described in an article by Mitchell and Flynn in
IEEE Design and Test of Computers, V5 N1 19-29, 2/88. It is also
briefly described in the infamous (?) IEEE Computer article "And Now a
Case for More Complex Instruction Sets", by Flynn, Mitchell, and Mulder;
V20 N9 9/87. Here, AWB is used to gather the performance data to advance
their (and I oversimplify) "CISC is better than RISC" claim.
paulf@ece-csc.ncsu.edu (Paul D. Franzon):
Cost (optional) $US50
It runs under X-windows on SUNs with 4.3bsd and DECs with Ultrix.
It is a lot of work to port to anything else.
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Advanced Micro Devices (AMD)
(Prem Sobel) prem@crackle.amd.com
I have developed, over a period of nearly 10 years, an architecture
simulation package which I now sell as a product. It has been used
by Vitesse Electronics (they ran out of money) to model their "new"
minisuper computer - where it helped find over 20 design errors.
The program is in 3 parts, the event manager, the human interface,
and the model section. An older version of the human interface has
been licensed to AMD for their internal architectural simulation.
It is written in C and is sold either all in source, or part in source.
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HELIX
Srikanth Nadhamuni <nss@silvlis.com>
I am presently working for a firm (Silvar-Lisco) which makes, event driven
behavioral simulators(Helix). Helix can basically simulate a schematic of
black boxes with the behavior of these black boxes described in HHDL (hier-
archical hardware description lang). Though it is mostly used for
simulating circuit design, it can perform simulation at any hierarchy,
be it gate level , FF level or at system level. It runs on Suns(SunOS),
Apollos(Ageis) and VAX(VMS).
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VHDL
Don Thomas <thomas@gauss.ece.cmu.edu>:
Your best bet is to go with the Verilog language available from
Gateway Design Automation Corp or a VHDL simulator.
Gateway address available upon request.
The System Architect's Workbench is a synthesis research project aimed
at automatically designing hardware from program-like descriptions
of the system to be built. We have used isps for years as input to
the system, but are now going to the Verilog and VHDL language. Latest
reference is ACM/IEEE Design Automation Conference 1988, under my name.
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SPARC
bwong@sun.com (Brian Wong)
Sun has a SPARC simulator package which is (I believe) currently
available. It's fairly generic, and as you might imagine, does run
in Sunview.
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End of summary.
--
____________________________________________________________________________
Bernhard Stockman Internet: bernhard@tds.kth.se
Computer Systems Architecture Laboratory (CSALAB)
Dep. of Tele Comm. and Computer Systems (TDS) Telephone: +46 8 790 90 25
The Royal Institute of Technology (KTH) Telefax : +46 8 24 77 84
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