ok@goanna.cs.rmit.oz.au (Richard A. O'Keefe) (09/04/90)
I have a question about the Intergraph CLIPPER chip. Unfortunately, the User's Manual I have dates from when it was the Fairchild CLIPPER, so my information may be out of date. The question is "what is the best way to test a few bits in a register"? What I'd like to do is if bit <A> of <R> is on then if bit <B> of <R> is on then on-on action else on-off action else if bit <B> of <R> is on then off-on action else off-off action. where <A>, <B>, and <R> are known at assembly time. The reason I raise this question here is that it touches on RISC design. At the price of sounding like Herman Rubin, it's something I've often had occasion to do, in code which was sufficiently critical to warrant hand-coding. On the VAX and Motorola 88k one has "branch to L if bit B of register R is set/clear", variously expressed. On several machines, there is a "move bit B of register R to the condition codes" instruction (RTPC, 68k, others) or a "set condition codes as if R := R & Mask had been done, but don't change R". I can't find anything obvious in the (*old*) CLIPPER manual. There may well be a way of doing it in current CLIPPER chips, which would suit me, but the RISC design question remains. If there is a spare register T, I can see how to test a bit by doing loadq #Mask, T ; register T := constant Mask andw R, T ; register T &= register R brne L ; goto L if register T not 0 If there aren't any registers spare, we can do it by rotating the bit in question to the sign bit, then rotating back. In my case, assuming that B > A, roti #(31-A),R brlt L_A_on roti #(A-B),R brlt L_A_off_B_on L_A_off_B_off: roti #(B-31),R ... L_A_off_B_on: roti #(B-31),R L_A_on: <obvious> With this scheme, the cost of the four-way dispatch is 2 conditional branches (irreducible) and three rotates, and the rotates are supposed to be single cycle, so I suppose I shouldn't complain too much. But can testing a bit in a register be so _very_ costly to provide that it pays to leave it out of a RISC? Surely it is asking a bit much to expect a compiler to rediscover tricks like the rotation trick. -- You can lie with statistics ... but not to a statistician.
rob@alice.coyote.trw.com (Robert Heiss) (09/05/90)
In article <3679@goanna.cs.rmit.oz.au> ok@goanna.cs.rmit.oz.au (Richard A. O'Keefe) writes: >I can't find anything obvious in the (*old*) CLIPPER manual. The newer C300 has the same instruction set as the older C100. >With this scheme, the cost of the four-way dispatch is 2 conditional >branches (irreducible) and three rotates, and the rotates are supposed >to be single cycle, so I suppose I shouldn't complain too much. From experimentation, on the C100 shifter instructions take a minimum of four cycles, plus one cycle per two bits of shift distance. Rotate by -2 is much faster than rotate by 30. But still slower than AND. LOADQ takes one cycle. ALU instructions such as ANDW and ANDI take from one to three cycles. Untaken branches are faster than taken ones. >But can testing a bit in a register be so _very_ costly to provide that >it pays to leave it out of a RISC? Surely it is asking a bit much to >expect a compiler to rediscover tricks like the rotation trick. Look on the bright side, CLIPPER gives you 15 fully general registers to play with. Finding a temporary register for the fast LOADQ-ANDW sequence should be easy. And it's compact too, only four bytes. ----- Robert Heiss rob@wilbur.coyote.trw.com