mmm@cup.portal.com (Mark Robert Thorson) (05/25/89)
The recent joke postings on SISC (Single Instruction Set Computers) remind me that I once heard the minimum instruction set of a computer is two: INC and BEQ. Of course, this assumes wraparound of the integer number space. Even with only two instructions, you can't quite use a single bit instruction word length, because both of these instructions take an absolute address as an argument. Along the same lines, I mentioned in sci.electronics that the Signetics 8X300 has a particularly sparse instruction set: only one arithmetic instruction, ADD, and two logicals, AND and XOR. You're expected to derive all the rest (e.g. INC, DEC, SUB, NEG, OR, COM) from these three.
trevor@ux.cs.man.ac.uk (Trevor Hopkins) (05/29/89)
This topic seems to come up (in comp.arch and elsewhere) about one a year, but I'll bite again anyway..... In article <18777@cup.portal.com> mmm@cup.portal.com (Mark Robert Thorson) writes: >The recent joke postings on SISC (Single Instruction Set Computers) remind They're no joke! >me that I once heard the minimum instruction set of a computer is two: No, the minimum number really is *one*. The instruction is `Reverse Subtract, Skip if Borrow' (RSSB), and the operand is given by a single memory address (a one-address format). Roughly, the operation says: `take the value from the memory at the address given, subtract it from the accumulator, putting the result both in the accumulator *and* back in the addressed location, and skip the next instruction if a borrow took place.' The code, of course, consists of a sequence of addresses, upon which to perform the RSSB instruction. This topic came up on USENET several years ago, and I was interested enough to suggest a final year (undergraduate) project to actually construct such a thing (called an OIC -- One Instruction Computer). The hardware worked well, using TTL technology and wire-wrap, with a clock (and instruction) rate of 16 MHz and 16-bit addresses and operands. I have the hardware in front of me as I type this message. The student also constructed a (macro) assembler, which took input in a vaguely PDP11-style (16-bit instructions only) and generated a sequence of RSSB instructions. This compination managed to execute `PDP11' type instructions at about 0.5 MIPS -- not too bad for a TTL single-board computer. A subsequent student started producing a Pascal compiler for the OIC, but with less success (he was a less able student :-). If anyone's interested, I can provide further information. Trevor. ------------------------------------------------------------------ Trevor P. Hopkins, Room 2.95, Department of Computer Science, University of Manchester, Oxford Road, Manchester, M13 9PL, U.K. Tel: (+44) 61-275 6170 Internal: 6170 JANET: trevor@uk.ac.man.cs.ux UUCP: ..ukc!man.cs.ux!trevor ------------------------------------------------------------------