[comp.arch] DMA and SCSI, Synchronous and not

daveh@cbmvax.UUCP (Dave Haynie) (09/13/89)

in article <22011@cup.portal.com>, cliffhanger@cup.portal.com (Cliff C Heyer) says:

> Sounds like Commodore is really *trying* to put out a "best" product...I wonder
> about many others. For example, IBM PS/2s always score the lowest in disk I/O. I
> assume this is because they want to *encourage* customers to shift the needed
> I/O BW to IBM big iron.

You apparently have to be real clever to get fast disk I/O on a PC, though 
I'm not at all sure just why.  Obviously an AT bus is limited to 2 MB/sec
transfers or thereabouts if you use the AT's DMA chip (and if it runs full
bus speeds).  The Commodore disk controllers are nothing magic, they're
basically just an honest attempt to get the most out of the available bus
bandwidth.  The new controller does this all in one custom DMA chip and
one SCSI chip; nothing the PC folks couldn't do for a built-in hard drive
controller, and on a 32 bit bit bus at 16MHz you'd be fully limited by what
your disk could manage.

> What about SYNCHRONOUS SCSI in the Amiga? (4.0MB/sec) Or DMA & memory 
> can't handle it at this speed(?)

Actually, the 4.0 Megs is a bit too fast; the Amiga bus goes around 3.5MB/s.
They are looking into Synchronous SCSI, though; the FIFOs would take care
of the speed differences anyway, I believe.  There's apparently something of
a software problem related to polling a drive for synchronous capability
that's held it up so far; I don't know any more details than that.

> Actually I must admit I don't know that much about the AT bus. 
> What is the AT bus rated at in aggregate and effective MB/sec throughput?

From what I've read and heard around, the AT bus basically maxes out at
4 MB/s, though it's implementation dependent.  It apparently doesn't permit
DMA masters, however, so all the "DMA" that happens on the bus is via the
AT's DMA controller chip.  Since that chip has to make two bus crossings to
transfer one datum, that tells me that the effective DMA speed is 2 MB/s,
and also that DMA isn't necessarily an advantage over programmed I/O, at
least as long as your DMA and programmed I/O are the full 16 bits wide (I
don't know much else on the AT DMA chip).

>  (For example, I assume it is
> 16 bits wide? Does this mean at 8 MHz it's aggregate throughput is 16MB/sec?

I think the bus requires at least 4 clocks/transfer, which would indicate
that the 8MHz bus (apparently the standard, though you could clock it 
faster) goes at the aforementioned 4MB/s.

> But I suppose because of DOS I/O is done via 8 bit bytes

Does it really have to go 8 bits at a time, even on a 16 bit bus.  That would 
tend to put a heavy damper on things.  Ick.  Amigas leave it up to the device 
driver.

> Cliff
-- 
Dave Haynie Commodore-Amiga (Systems Engineering) "The Crew That Never Rests"
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