[comp.arch] HyperStone info desired

ouij@xurilka.UUCP (exhausted jazz surfer) (08/14/90)

Would anybody happen to have information
concerning a new chip being developed
in germany known as HyperStone?  

All I have seen is the small blurb in the may 90
issue of unix world.  

Apparently, these researchers in Germany have
taken a hybrid approach between CISC vs RISC.
              
an interesting note  which may furthur fuel
this weeks side arguement of  `32 vs 64bits'. 
HyperStone supposedly is mainly a RISC design
with a 32 bit word, except for instructions
where only 16 are used.  Thus halving the bus access.  

The blurb claims that the chip currently runs
at 25 Meaningless Instructions Per Second
and claim that it will hit 150 in the near
future.  

And I appreciate any pointers towards
more info.

Ouij
Ubangi Research Inc
ouij@xurilka.uucp
				``And Love,
				     a burnt match, skating a urinal''