RWilson@acorn.co.uk (07/25/89)
In the recent articles on Rounding Modes in IEEE arithmetic, Lawrence Crowl and Herman Rubin have got around to discussing the chicken and egg problem: if hardware continues to think of the IEEE rounding as "MODES" and puts them in "status registers" rather than as part of the instruction, then the software folk will continue not to write languages which use these desireable facilities. Well us hardware folks (Acorn) have come to your rescue: the floating point system for the Acorn RISC Machine (VLSI Technology VL86C010 and VL86C020) provides the rounding modes as part of the instruction. There is both a hardware and a software implementation of it. Full details have been emailed to Lawrence (since he put his foot in it first), so email him [or me if you are really stuck] for more. One little thing: ARM based computers start at 649 pounds in the UK. And you can't buy them in the states at all. Must be something in your culture which doesn't want control over rounding modes :-)! --Roger Wilson
daw@cbnewsh.ATT.COM (David Wolverton) (07/27/89)
In article <817@acorn.co.uk>, RWilson@acorn.co.uk writes: > Well us hardware folks (Acorn) have come to your rescue: the floating point > system for the Acorn RISC Machine (VLSI Technology VL86C010 and VL86C020) > provides the rounding modes as part of the instruction. ... > > One little thing: ARM based computers start at 649 pounds in the UK. And you > can't buy them in the states at all. Must be something in your culture > which doesn't want control over rounding modes :-)! > > --Roger Wilson Sorry to burst your bubble Roger, but the AT&T WE32206 Math Acceleration Unit chip provides BOTH modes AND per-instruction rounding. For instance, you could set the '206 to the "round to nearest" mode, then if necessary override the current mode for an instruction or two. I wrote an assembler for this chip that accepted an optional rounding mode suffix on each floating-point instruction. Thus, if "mfaddd" is a double-precision addition, "mfaddd.rz" forces the addition to be rounded to zero, regardless of the current rounding mode. This chip is in the newest AT&T 3B2 models, but I don't think the production assembler supports this feature of the WE32206. Dave Wolverton AT&T daw@attunix.att.com
frazier@oahu.cs.ucla.edu (Greg Frazier) (07/28/89)
In article <2620@cbnewsh.ATT.COM> daw@cbnewsh.ATT.COM (David Wolverton) writes: >In article <817@acorn.co.uk>, RWilson@acorn.co.uk writes: >> Well us hardware folks (Acorn) have come to your rescue: the floating point <deleted> >> One little thing: ARM based computers start at 649 pounds in the UK. And you >> can't buy them in the states at all. Must be something in your culture >> which doesn't want control over rounding modes :-)! > >Sorry to burst your bubble Roger, but the AT&T WE32206 Math Acceleration >Unit chip provides BOTH modes AND per-instruction rounding. For instance, <deleted> >This chip is in the newest AT&T 3B2 models, but I don't think the production >assembler supports this feature of the WE32206. > Well, Dave, you are going to have to explain to us how this bursts the Acorn folks' bubble. They have produced a high-performance RISC processor which supports the rounding modes that everybody's been talking about. He (Roger) didn't make any claims other than that, and the fact that us 'mericans do not import ARM's. ATT, on the other hand, has an FP accelerator which supports these rounding modes, but it is only used in a processor whose machine language doesn't support them - the exact problem everybody's been complaining about! Some bubble-burster you are... :-) Greg Frazier &&&&&&&&&&&&&&&&&&###################***************** Greg Frazier o Internet: frazier@CS.UCLA.EDU CS dept., UCLA /\ UUCP: ...!{ucbvax,rutgers}!ucla-cs!frazier ----^/---- /
daw@cbnewsh.ATT.COM (David Wolverton) (07/28/89)
> In article <2620@cbnewsh.ATT.COM> daw@cbnewsh.ATT.COM (David Wolverton) writes: > >This chip is in the newest AT&T 3B2 models, but I don't think the production > >assembler supports this feature of the WE32206. to which Greg Frazier writes: In article <26067@shemp.CS.UCLA.EDU>, frazier@oahu.cs.ucla.edu (Greg Frazier) writes: > ... ATT, on the > other hand, has an FP accelerator which supports these > rounding modes, but it is only used in a processor whose > machine language doesn't support them - the exact problem > everybody's been complaining about! Some bubble-burster > you are... :-) Well, to be picky, I said the "assembler" didn't support them. The machine language of the WE32x00 CPUs does support the rounding feature. To get the production assembler to "do the right thing," you would have to generate the floating point instructions using a somewhat less mnemonic alternate interface. I.e. instead of the mfaddd.rz %f0,%f1,%f2 instruction described in my previous note, you'd have to do something like SPOPD ADD|F0SRC|F1SRC|F2DST|RZ with approprite macro definitions for ADD, F0SRC, etc. BTW, SPOPD stands for Support Processor OPeration, Double precision. And all this is true for a chip that has been commercially available in the US for at least 2 years. Dave Wolverton daw@attunix.att.com