feustel@well.sf.ca.us (David Alan Feustel) (11/17/90)
The 386 and 486 are advertised as having 46 bit addressing and 4
gigabyte segment length capability. This overstates their capabilities
slightly, since the mapping of all segments into the single 32 bit virtual
address space implemented in the 386 and 486 imposes the restriction
that the sum of the length of the code, data and stack segments must be
less than or equal to 4 gigabytes (ignoring the degenerate case of all
descriptors pointing to the same memory).
True 46 bit memory addressing can be easily designed into the Intel 586
chip. This would permit the simultaneous access by the 586 of multiple
4 gigabyte segments, a capability not currently possessed by the 386 or
486.
46 bit addressing could be implemented by making the use of the
base address of a descriptor dependent upon the state of bit 21 of dword
2 (currently available) in the segment descriptor.
If that bit is 0 then the 586 works just like a 486; if that bit is one
and paging is enabled, then the descriptor base address is used instead
of the value of CR3 as the page directory base register for this memory
reference.
This paging algorithm effectively allows each segment to have its own
page table. It also permits segment lengths to change without requiring
the relocation of other segments, since no other segments would be sharing
this segment's 32 bit address space.
A further enhancement to increase performance would be to add a register
holding the appropriate CR3 register value to the invisible register set
associated with each of the 6 segment registers.
Shall we take a vote?
--
Dave Feustel, 1930 Curdes Ave, Fort Wayne, IN 46805-2710 (219)-482-9631
EMAIL: feustel@well.sf.ca.us {ucbvax,apple,hplabs,pacbell}!well!feustel
BIX: feustel COMPUSERV: 72730,566 MCIMAIL: dfeustel seanf@sco.COM (Sean Fagan) (11/19/90)
In article <21691@well.sf.ca.us> feustel@well.sf.ca.us (David Alan Feustel) writes: >The 386 and 486 are advertised as having 46 bit addressing and 4 >gigabyte segment length capability. This overstates their capabilities >slightly, since the mapping of all segments into the single 32 bit virtual >address space implemented in the 386 and 486 imposes the restriction >that the sum of the length of the code, data and stack segments must be >less than or equal to 4 gigabytes (ignoring the degenerate case of all >descriptors pointing to the same memory). Uhm, no, it doesn't. Take a look at how memory management is done on the *86 again, and you'll see a couple of different ways you can do it. Now, it's not *easy*, not by a long shot. And you end up having to swap lots of different things out, completely. But you can do it. It's just not worth the bother (IMNSHO). Also, I don't believe you can get 46-bit addressing completely. The chip can have a total of 46-bit virtual addresses, but some of those are going to be for ring 0, some for ring 1, etc. -- -----------------+ Sean Eric Fagan | "*Never* knock on Death's door: ring the bell and seanf@sco.COM | run away! Death hates that!" uunet!sco!seanf | -- Dr. Mike Stratford (Matt Frewer, "Doctor, Doctor") (408) 458-1422 | Any opinions expressed are my own, not my employers'.
feustel@netcom.UUCP (David Feustel) (11/20/90)
I doubt even one fullsized 386 segment can be used on a 386 since at least 2 segments are required to execute in protected mode; however, I would be happy to be shown to be wrong. Please demonstrate without aliasing any segments. -- David Feustel, 1930 Curdes Ave, Fort Wayne, IN 46805, (219) 482-9631
johnl@iecc.cambridge.ma.us (John R. Levine) (11/21/90)
In article <8833@scolex.sco.COM> you write: >In article <21691@well.sf.ca.us> feustel@well.sf.ca.us (David Alan Feustel) writes: >>[The 386 and 486 don't really have the alleged 46 bit addressing because] >> the mapping of all segments into the single 32 bit virtual address space >>... imposes the restriction the sum of the length of the code, data and >>stack segments must be less than or equal to 4 gigabytes ... > >Uhm, no, it doesn't. Take a look at how memory management is done on the >*86 again, and you'll see a couple of different ways you can do it. Really, it does. The 386 has six segment registers offering up to six simultaneously addressable segments. All six addressable segments must be mapped into the 32 bit linear address space (loading a segment register fails if you try to load a not-present segment, and the operating system has to map it before the process can continue.) Remember that the paging happens underneath the linear space -- a segment is either mapped into the linear space entirely or not at all. In practice this either means that you restrict each segment to 29 bits, so you can map them by fiddling page directories and reserve 1/8 of the linear space for each segment, or more commonly require that the entire set of mappable segments map into 32 bits. Also remember that if you have an operating system, it has to be mapped into the linear space as well so it can take traps and system calls. Even if a scheme that maps segments in and out works in theory, it is likely to have dreadful performance since traps and page table manipulation are slow. >Also, I don't believe you can get 46-bit addressing completely. The chip >can have a total of 46-bit virtual addresses, but some of those are going to >be for ring 0, some for ring 1, etc. The segment number is 16 bits, but two of those are the ring number, leaving 14 segment number bits plus 32 bit intrasegment addresses makes 46. One might say it's more meaningful to say 45 bits per process plus a 45 bit global address space (another segment bit is the local/global bit) but that's a relative nit. Regards, John Levine, johnl@iecc.cambridge.ma.us, {spdcc|ima|world}!iecc!johnl
seanf@sco.COM (Sean Fagan) (11/21/90)
In article <17126@netcom.UUCP> feustel@netcom.UUCP (David Feustel) writes: >I doubt even one fullsized 386 segment can be used on a 386 since at >least 2 segments are required to execute in protected mode; however, Obviously, you cannot have more than one complete segment in memory at once. However: you *can* page portions of each segment out of memory. The problems (that I alluded to) come into play when you have to manage the pages. You need to mark lots and lots of pages as not-present, and, when you do swap them in, you need to make sure that no other segment has that physical location marked as belonging to it. Basicly, what you have now, but on a far larger order. I won't get into what happens when you have more than one task, though... -- -----------------+ Sean Eric Fagan | "*Never* knock on Death's door: ring the bell and seanf@sco.COM | run away! Death hates that!" uunet!sco!seanf | -- Dr. Mike Stratford (Matt Frewer, "Doctor, Doctor") (408) 458-1422 | Any opinions expressed are my own, not my employers'.
feustel@netcom.UUCP (David Feustel) (11/25/90)
Keep in mind that the virtual paging address space into which ALL segments must be mapped if they are accessible is only 2**32 bytes. If a segment 2**32 bits long is mapped into that space there is no address space left to map any other segments. -- David Feustel, 1930 Curdes Ave, Fort Wayne, IN 46805, (219) 482-9631 EMAIL: netcom.uucp
hays@isc.intel.com (Kirk Hays) (12/01/90)
>I doubt even one fullsized 386 segment can be used on a 386 since at >least 2 segments are required to execute in protected mode; however, >I would be happy to be shown to be wrong. Please demonstrate without >aliasing any segments. That's too easy - just have a single code segment, and never load any of the other segment registers with anything but 0. Write a program that does only reads from memory, never writes to memory, never calls, never pushes or pops, never switches tasks, and never interrupts. The spoiler, of course, is the need for areas for page tables, gdt, tss... With enough effort, though, you can work around this, too. Once you're bootstrapped into 32 bit mode, and you're done loading segment registers, and interrupts are disabled, all the tables can be discarded. I wrote one of these once, as a special purpose black-box, which received input through the io ports, manipulated it in the registers, did a lookup in a big memory table, and wrote the result back through the io ports. It didn't require 4GB of memory, but similar applications could. RAM was used only during initialization, ROM was mapped into low memory by writing a port after initialization. A giant state-machine router. >-- >David Feustel, 1930 Curdes Ave, Fort Wayne, IN 46805, (219) 482-9631 I'm an i860 man, now... -- Kirk Hays - NRA Life. People should be enabled, not dependent - guns are an enabling technology.