SFurber@acorn.co.uk (05/09/89)
aglew@mcdurb.Urbana.Gould.COM writes: > Apparently the ARM does something similar, only checking for interrupts > at branches. This is not correct. ARM checks for interrupts at the end of each and every instruction. The store multiple register instruction allows a warped sort of semaphore instruction to be built, and the new ARM3 (VL86C020) has an uninterruptable memory to register SWAP instruction for just this purpose. Steve Furber sfurber@acorn.uucp Acorn Computers Ltd, England.
jhallen@wpi.wpi.edu (Joseph H Allen) (05/10/89)
In article <759@acorn.co.uk> SFurber@acorn.co.uk writes: >This is not correct. ARM checks for interrupts at the end of each and every >instruction. The store multiple register instruction allows a warped sort of >semaphore instruction to be built, and the new ARM3 (VL86C020) has an >uninterruptable memory to register SWAP instruction for just this purpose. >Steve Furber sfurber@acorn.uucp > Acorn Computers Ltd, England. Speaking of warped semaphores, a nifty test-and-set instruction can be made on machines (like 6809 where I originally used it) which have rotate memory: Lock a resource: wait: ror lock bcc wait Release a locked resource: inc lock This will even work in multiple-CPU situations as long as bus ownership doesn't change in read-modify-write instructions (yes, I did write a multi-tasking OS on an 8-bit processor- interrupts caused a task switch) - - - - - On a different note, how difficult is offset optomizations for machines (like the ARM and most other RISC processors, I think) with offsets which are smaller than the address space? With the ARM, I notice that the lower 2 address bits are output. Could these be used to interrupt the processor for handling misaligned words? (yes, I did just get ARM chip info and I'm thinking of doing something neat with this $45 dollor 32 bit chip- I also see that VLSI is planning to make 20Mhz and 32Mhz versions... a 32Mhz version would faster than SPARC...)
aglew@mcdurb.Urbana.Gould.COM (05/10/89)
>aglew@mcdurb.Urbana.Gould.COM writes: > >> Apparently the ARM does something similar, only checking for interrupts >> at branches. > >This is not correct. ARM checks for interrupts at the end of each and every >instruction. The store multiple register instruction allows a warped sort of >semaphore instruction to be built, and the new ARM3 (VL86C020) has an >uninterruptable memory to register SWAP instruction for just this purpose. > > >Steve Furber sfurber@acorn.uucp > Acorn Computers Ltd, England. Sorry, I confused the Transputer with the Acorn.
roger@wraxall.inmos.co.uk (Roger Shepherd) (05/12/89)
In article <28200309@mcdurb> aglew@mcdurb.Urbana.Gould.COM writes: >>aglew@mcdurb.Urbana.Gould.COM writes: >>> Apparently the ARM does something similar, only checking for interrupts >>> at branches. >>Steve Furber sfurber@acorn.uucp >Sorry, I confused the Transputer with the Acorn. This isn't true for the Transputer either. The transputer checks for interrupts at the end of every instruction (and during some too). However, the transputer only TIMESLICES low priority processes on unconditional jumps and ``loop end'' instructions. Roger Shepherd, INMOS Ltd JANET: roger@uk.co.inmos 1000 Aztec West UUCP: ukc!inmos!roger or uunet!inmos-c!roger Almondsbury INTERNET: @col.hp.com:roger@inmos-c +44 454 616616 ROW: roger@inmos.co.uk