jsweedle@mipos2.intel.com (Jonathan Sweedler) (11/08/90)
I recently read (in a translation from an article in a Japanese
magazine) that Sharp will be sampling a 32 bit non-von Neumann
microprocessor that was jointly developed with several Japanese
companies and Osaka University's Professor Terada. The article says the
processor is a "data drive processor [that] consists of four chips...
Each chip performs 20 mil operations/sec 5-10 times faster than
conventional von Neumann processors. Sharp plans to hold seminars
across the country between Nov. and March."
Does anybody know anything about this processor? How did they design this
to get around the von Neumann bottleneck? What kind of memory system
does it require. etc. etc.
===============================================================================
Jonathan Sweedler, Microprocessor Design, Intel Corp.
UUCP: {decwrl,hplabs,oliveb}!intelca!mipos3!mipos2!jsweedle
ARPA: jsweedle%mipos2.intel.com@relay.cs.net