carters@ajpo.sei.cmu.edu (Scott Carter) (04/19/91)
In article <00947104.8B2D8080@KING.ENG.UMD.EDU> sysmgr@KING.ENG.UMD.EDU (Doug Mohney) writes: >In article <32580016@hpcuhe.cup.hp.com>, linley@hpcuhe.cup.hp.com (Linley Gwennap) writes: >> While HP's IC >>fabrication processes are very good, they are not out on the "bleeding >>edge", so there's plenty of room for future improvement. (For bleeding >>edge, try TI's 0.8 micron BiCMOS process!) > >Can you (without lotta headaches) put HP-PA on Gallium Arsenide <sp>? > There are some problems in building current High-end RISCs in GaAs :) Note that it hasn't quite happened yet, modulo the late lamented Prisma. At 250 MHz the speed of light ain't what it used to be. Chip crossings become much more expensive (for lots of reasons) relative to gate times. See reference below for what one must go through to support a single latency off-chip cache. Also, in many GaAs technologies you have much less freedom to build special drivers for high [onchip] fanouts (hence my comment that in some technologies and architectures 64-bit integers can have critical path effects, and I don't mean the extra gate in the carry tree [e.g. driving bypass select muxes late in the cycle]). Various factors in existing high-integration GaAs processes suggest that GaAs implementations of existing architectures may not be as fast as one would expect, or alternatively that an architecture designed for GaAs might have some differences from one designed for CMOS. See below if you want gory details, otherwise hit 'n' - [the following is based on moderately recent reading, and having been one of the team on the McDonnell Douglas DARPA GaAs micro - any errors in describing other companies' technologies are purely my own and quite unintentional] In MESFETs (e.g. Vitesse), you basically can't build a pass transistor. Some problems follow :{ notably, lots of datapath assumptions change when you don't have tristate busses. Still, Vitesse has [claimed to] achieve[d] gate counts, (300K gate array!) densities, etc., which make it feasible in theory to build at least an R3000 (see January 91 IEEE Computer - don't have reference at hand but it's Mudge, ...,.., and Milano). In enhancement JFET DCFL (e.g. SONY) you avoid some of the above problems, but the falloff in gate speed with capacitive load is awful (see Kawasaki, et al, 1990 IEEE GaAs IC Symposium, pp 135-138), and the only circuit they have published is a 10K gate array (they use a 1V logic level which has caused us [in our JFET process, not SONY's!] mucho problems in building SRAMs of the speed one would otherwise expect). The power consumption of a loaded gate, even if it never switches, is not so good, so again some of the architecture issues may have different tradeoffs. Still, they have 0.5u lengths and 3-level metal with 2um width and spacing, so it's certainly feasible to build a RISC core in this process. In bipolar heterojuntion GaAs (e.g. TI - think of it as the GaAs equivalent of I2L [but don't dismiss it! :)]), one gets great speeds, very good drive, but since it's a pure current-mode logic the amount of RAM one can put on a die is limited (without heroic cooling measures) :{. > Signature envy: quality of some people to put 24+ lines in their .sigs > -- > SYSMGR@CADLAB.ENG.UMD.EDU < -- Scott Carter - McDonnell Douglas Electronic Systems Company carter%csvax.decnet@mdcgwy.mdc.com (preferred and faster) - or - carters@ajpo.sei.cmu.edu (714)-566-5741 The opinions expressed herein are solely those of the author, and are not necessarily those of McDonnell Douglas.
linley@hpcuhe.cup.hp.com (Linley Gwennap) (05/04/91)
(Ajay Shah) writes: > BTW, I just saw a SPARC clone built by Xerox at a USC Sun computer > fair. That sounds rather important to me -- isn't a clone by > Xerox big news?? ---------- Xerox copies? Big news? Naaaah! :-) --------------------------------------------------------------------------- DISCLAIMER: The views expressed here do not Linley Gwennap represent the views of the Hewlett-Packard PA-RISC Marketing Company. Caveat emptor. Hewlett-Packard