daver@hcx2.SSD.HARRIS.COM (01/12/88)
The MC68020 provides a Memory Indirect Post-indexed addressing mode. Referring to the 2nd edition of the User's Manual, the last paragraph of page 2-10 indicates that "all four user-specified values are optional." Does this mean that an addressing mode (described on the next page) could be written as: ([bd,An], , ) ? How would the extension word for this be encoded? According to pages 2-19 and 2-20, it would seem reasonable to set the Index Suppress (IS) bit to '1' and the Index/Indirect Selection (I/IS) bits to '101'. But Table 2-2 says that such a combination is 'Reserved.' Are all four user-specified values really optional? What does the hardware do when it sees this particular reserved value? (The preliminary version of the MC68030 User's Manual seems to say the same thing as the MC68020 manual in this area.)
bcase@apple.UUCP (Brian Case) (01/14/88)
In article <93900009@hcx2> daver@hcx2.SSD.HARRIS.COM writes: > >The MC68020 provides a Memory Indirect Post-indexed addressing mode. > >Referring to the 2nd edition of the User's Manual, the last paragraph of >page 2-10 indicates that "all four user-specified values are optional." >Does this mean that an addressing mode (described on the next page) could >be written as: ([bd,An], , ) ? >How would the extension word for this be encoded? According to pages 2-19 >and 2-20, it would seem reasonable to set the Index Suppress (IS) bit to '1' >and the Index/Indirect Selection (I/IS) bits to '101'. But Table 2-2 says >that such a combination is 'Reserved.' > >Are all four user-specified values really optional? What does the hardware >do when it sees this particular reserved value? (The preliminary version of >the MC68030 User's Manual seems to say the same thing as the MC68020 manual >in this area.) Ah, yes!! I have been through this before. A related question is: "How can you specify indirection through a data register? I.e., how does one encode MOVE (Dn),Dn ???" Well, using various combinations of supression, simple data register indirection can be encoded on the 68020. To answer your question, yes, all four user-specified values are optional! So, to encode what you have written ([bd,An],,), you would set IS to 1 and set I/IS to 001. To encode the simple data register indirection, one would set BS to 1, IS to 0, I/IS to 000, and BD SIZE to 01. Then set D/A to 0, REGISTER to the desired data register number, W/L to 1 (unless you want a 16-bit pointer), and SCALE to 00. Don't ask me how many cycles these stupid addressing modes take, I get nauseous at the thought. Good luck 68040.
brucek@hpsrla.HP.COM (Bruce Kleinman) (01/15/88)
+------- | Don't ask me how many cycles these stupid addressing modes take, I get | nauseous at the thought. Good luck 68040. +------- I don't know about the 68040, but I have some numbers for the '030. Quoting from the depths of the 68030 User's Manual, section 11.6.1, the Fetch Effective Address Table. This table "indicates the number of clock periods needed for the processor to caclulate and fetch the specified effective address." Hence, instruction execution is not included. I-Cache Case 12 cycles No-Cache Case 14 cycles Now if they can only design a 16-stage pipeline for the 68040, we'll have single cycle execution AND backward compatibilty :-) Bruce Kleinman ( brucek%hpnmd@hplabs.hp.com )