[comp.arch] Floating Point Multipliers

ranga@uceng.UC.EDU (Dr. Ranga R. Vemuri) (03/04/90)

Does any one have pointers to info. on floating point arithmetic units
(multipliers and dividers in particular) implemented in CMOS or
NMOS.  I  am particularly looking for information on single chip 
implementations and their performance (area, speed etc...).

- Ranga.


-- 
Dr. Ranga Vemuri                                     ranga@uceng.uc.edu
Laboratory for Digital Design Environments           (513)-556-4784
M.L. 30, Dept. Electrical & Computer Engineering     (513)-556-4769  
University of Cincinnati, Cincinnati, OH 45221, USA

lindsay@MATHOM.GANDALF.CS.CMU.EDU (Donald Lindsay) (03/05/90)

In article <3880@uceng.UC.EDU> ranga@uceng.UC.EDU (Dr. Ranga R. Vemuri) writes
>Does any one have pointers to info. on floating point arithmetic units
>(multipliers and dividers in particular) ...

If your library has a year's worth of "EDN" and "Electronic Design"
(etc), then you should be able to get all the phone numbers with a
few minutes work.

The hottest vaporware I know of is the new "130" series from BIT.
Soon, you can get a sample with a 100 MHz double precision pipeline.
They're also claiming that flowthrough only has one stage of latency:
wow. Of course, the package is 5 square inches ...  $1400 ... and
thirty watts. Hot, indeed.
-- 
Don		D.C.Lindsay 	Carnegie Mellon Computer Science