naim@eecs.nwu.edu (Naim Abdullah) (05/17/89)
Can anybody provide a ball park figure for a feature size that will cause
quantum mechanical tunneling effects to cause a chip to malfunction ?
In other words, what is the lower bound on the feature size imposed by
q-m tunneling ? How far away are we from it ?
Please excuse the naive question. I am sure you comp.arch people have beaten
this horse many times, but I am just a software person looking in.
Thank you.
Naim Abdullah
Dept. of EECS,
Northwestern University
Internet: naim@eecs.nwu.edu
Uucp: {oddjob, chinet, att}!nucsrl!naimstein@pixelpump.osc.edu (Rick 'Transputer' Stein) (05/18/89)
In article <3810043@eecs.nwu.edu> naim@eecs.nwu.edu (Naim Abdullah) writes: >Can anybody provide a ball park figure for a feature size that will cause >quantum mechanical tunneling effects to cause a chip to malfunction ? > >In other words, what is the lower bound on the feature size imposed by >q-m tunneling ? How far away are we from it ? Back when I was a undergraduate, I did some metal-insulator-metal and metal-insulator-superconductor electron tunneling studies. Naturally, to examine features such as density of states, and quasi-particle distributions in these structures, one had to prepare a sample which was robust enough and possessed the correct dimensions. Back in the Low Temp Lab at UC Irvine, one could make sample after sample for days or weeks on end which yielded no results or just didn't plain work. But when you were successful, you measured the hell out it. Anyways, to answer your question about how big a tunneling structure must be, I'd say that about 300 Angstroms for each electrode, separated by an oxide or some other insulator layer of about 20-30 angstroms is the limit. I conclude this based on my interferometric measurements of the junction structure. A thinner dimension on either electrode was generally not electrically continuous, although one could use a "cold fab" technique whereby one cooled the substrate to liquid nitrogen temperatures and vacuum evaporated a layer. This technique usually prevented "islands" from cropping up along the electrode, and tended to make it continous. The thing that always got me about building tunneling junctions was how the local smog concentration affected the production process. Maxwell's demon is alive and well in the experimental low temp. solid state physics world that I used to know. >Thank you. Your welcome. -=- Richard M. Stein (aka Rick 'Transputer' Stein) Office of Research Computing @ The Ohio Supercomputer Center Ghettoblaster vacuum cleaner architect and Trollius semi-guru Internet: stein@pixelpump.osc.edu
jjb@sequent.UUCP (Jeff Berkowitz) (05/22/89)
In article <3810043@eecs.nwu.edu> naim@eecs.nwu.edu (Naim Abdullah) writes: >Can anybody provide a ball park figure for a feature size that will cause >quantum mechanical tunneling effects to cause a chip to malfunction ? > I recommend "Introduction to VLSI Systems", Mead & Conway, Addison-Wesley, 1980. This old book is still a good way for people without a background in semiconductors to at least get some appreciation of the issues. In chapter 1 Mead writes Finally, there appears to be a fundamental limit of approximately one-quarter micron channel length, where certain physical effects such a the tunneling through of the gate oxide...begin to make devices of smaller dimension unworkable. Chapter nine has a more extensive discussion of the limits to scaling. -- Jeff Berkowitz N6QOM uunet!sequent!jjb Sequent Computer Systems Custom Systems Group