zs01+@andrew.cmu.edu (Zalman Stern) (02/28/90)
[Donald Linsday described the RS/6000 virtual memory segmentation model.] As far as I can tell, the best use for segment registers on the RS/6000 is to get a 24 bit process ID tag in the virtually addressed cache. (One needs 16 segment ids per process to get 4 Gigabytes of addressable memory per process so the 28 bits goes down to 24) User programs are going to have a hard time taking advantage of more than 32 bits worth of address space since the segment registers are not visible to non-priveleged processes. I suppose the OS could provide a system call to load a segment register. User programs would then have 28 bit pointers and use them as offsets to a base register which had the segment register in the top 4 bits and zeros in the low 28 bits. (Maybe that is why the POWER arch. has a base reg. + index reg. addressing mode...) The RS/6000 MMU (Rosetta) also has support for "transaction" locks on 128 byte regions of memory. An extension from the RT's MMU is that the TLB hardware can grant read or write locks automatically. (If anybody is interested, I can post more info.) By now, the TLB stuff is hairy enough that software TLB reload is out of the question. (The TLB has 128 entries and is 2 way set associative. There are separate TLBs for instructions and data.) It would be interesting if someone from HP could post a description of the HP-PA MMU. It is a good contrast since I believe HP-PA has segmentation and an inverted page table like the RS/6000, but they have user visible segment registers and software TLB reload. Sincerely, Zalman Stern Internet: zs01+@andrew.cmu.edu Usenet: I'm soooo confused... Information Technology Center, Carnegie Mellon, Pittsburgh, PA 15213-3890