lamaster@pioneer.arpa (Hugh LaMaster) (08/27/87)
I would like to introduce a new topic for discussion. The preliminary
documentation on the Weitek chip set has been out for 2 or 3 months. I don't
know if they are shipping samples yet, but I have read the documentation. I
am very impressed. I see this chip set as being the first in a new era of
floating point capable microprocessor systems. For those who haven't seen any
of the announcements, the 8000, 8032, and 8064 are a set of three processors
in the same family. The 8064 is a two chip 64 bit floating point version.
Interesting features:
1) Separate code and data buses :-)
2) 64 bit wide data bus on the 8064 :-)
3) 64 bit wide floating point registers on the 8064 (32 of them) :-)
4) A "medium long instruction word" instruction format, with separate program
control, integer, and floating point fields, allowing simultaneous issue of
compare/branch, load/store and integer arithmetic, and floating point
arithmetic.
5) A shuffle instruction which can turn just about any brain-damaged bit/byte
order into any other in 1 or 2 instructions
6) A claimed 7 MIPS (11/780 = 1) on scalar code, and 2 MFLOPS on Linpack (peak
register to register higher). It would appear that 10 MFLOPS sustained on
certain vector floating point operations may be feasible, though it doesn't
have a vector instruction set, due to the simultaneous load/store and floating
point instruction issue. Very cute.
The processor set includes no instruction cache or MMU :-( or data cache :-)
Unfortunately, the machine is little-endian :-(
but the shuffle instruction almost makes up for it :-)
From the standpoint of us numerical simulation bigots, this machine has just
about the right balance between integer and floating point performance. In
fact, if it turns out the way it is documented now, it should be about 2/3 of
a CDC 7600, scalar and vector. Just what I need in a high performance
workstation.
I assume that some companies out there are designing it in to their systems-
and I eagerly await the results. Does anyone know anything more than the
above, or have more complete or correct information?
Hugh LaMaster, m/s 233-9, UUCP {seismo,topaz,lll-crg,ucbvax}!
NASA Ames Research Center ames!pioneer!lamaster
Moffett Field, CA 94035 ARPA lamaster@ames-pioneer.arpa
Phone: (415)694-6117 ARPA lamaster@pioneer.arc.nasa.gov
"IBM will have it soon"
(Disclaimer: "All opinions solely the author's responsibility")