zdenko@csd4.milw.wisc.edu (Zdenko Tomasic) (10/29/87)
Does anybody have any hands-on (or otherwise) experience with the Astronautics ZS-1 superminicomputer? It is a 45 MIPS (which?), 22.5 MFLOPS pipelined (nonvector) machine with 32-256 MB of real memory(16-way interleaved) and support for 4GB virtual one(64KB page). OS is modified 4.3BSD with NFS. Bus: Multibus I with up to 32 I/O processors, running Artos, a real time I/O kernel in addition to the regular CPU BSD kernel. Disk striping through virtual drives. Aggregate bandwiths to peripherals is 45MB/s. 64-bit word size (supports 32 also). Some people here at UWM wonder what it is like , so send your comments, experiences, flames, etc. by e-mail to me and I'll summarize if there is any interest. Tnx. Zdenko Tomasic UWM, Chem. Dept. Milwaukee,WI,53201 __________________________________________________________ UUCP: ihnp4!uwmcsd1!csd4.milw.wisc.edu!zdenko ARPA: zdenko@csd4.milw.wisc.edu __________________________________________________________
ram%shukra@Sun.COM (Renu Raman, Sun Microsystems) (10/30/87)
In article <3322@uwmcsd1.UUCP>, zdenko@csd4.milw.wisc.edu (Zdenko Tomasic) writes: > Does anybody have any hands-on (or otherwise) experience with > the Astronautics ZS-1 superminicomputer? would paper info be OK? > Look into "The ZS-1 Central Processor" that appeared in the conference on ASPLOS (Architectural Support for Programming languages and Operating Systems). The MIPS/FLOPS/MEM figures you quoted appear on the paper. The technology is very very conservative - off-the-shelf Schottky MSI & SSI. So, significant speed-ups can be seen with custom VLSI. The instruction stream is split into Fl. pt & non-flt. pt. 1. Load & Store queues for CPU-Mem communication. There are a pair of queues, one for a 32 bit register file (integer registers Called as A) and one of 64 bit register file (Flt. Pt. registers -called as X). The A's load queue is 15 element deep and store 7 (I guess 2 source -> 1 dest). Likewise the X section has 15 for load and 7 for store. 2. Pagesize = 64K 3. Instruction fetch has 16K instruction cache. The main thrust is towards dynamic instruction scheduling(which I like) as opposed to Static alone in many RISCs, Multiflow's VLIW. Much like RISC Vs CISC, it promises to raise the issue of Static Scheduling Vs Dynamic Scheduling - which could well be the next wave in the uP arena (when more Si is available for more functional units ). In the paper they barely touch on the religious issues of added delay in Critical Paths & hardware complexity Vs REAL performance improvement. But this is probably the first case where CDC & CRAY's Scoreboarding has moved into the minisuper class and wonder when it will enter the micro. The other interesting issue is that both instruction streams (A & X) need not go in lock-step fashion due to split intstruction stream and HW which allows instruction bypassing within a stream - tends to show data-flowisms[In Multiflow's case, I believe its lockstep]. Contrasting to the Multiflow machine where the compiler that was optimized for one set of application need to do a good job with another as localised instruction level parallelism varies from application to application - here dynamic scheduling added with static re-organization will be a big win. On the issue of dynamic scheduling(CDC's scoreboarding, reservation stations), there have been a number of papers, starting with Tomasulo (way back in 67 I think), Thornton, Horng (ATT) and by Weiss (The designer of ZS-1). I have barely touched the details and I sure John Wardale & others at Astronautics can say more about this (& correct me if I am wrong anywhere) --------------------- Renu Raman ARPA:ram@sun.com Sun Microsystems UUCP:{ucbvax,seismo,hplabs}!sun!ram M/S 5-40, 2500 Garcia Avenue, Mt. View, CA 94043
ram%shukra@Sun.COM (Renu Raman, Sun Microsystems) (10/31/87)
In article <32465@sun.uucp>, ram%shukra@Sun.COM (Renu Raman, Sun Microsystems) writes: > be a big win. > (way back in 67 I think), Thornton, Horng (ATT) and by Weiss (The designer > of ZS-1). > SOme correction: For Horng - Read Torng. (coauthors Acosta & Kjelstrup) For Weiss - Read J.E.Smith (Weiss was his Student ) --------------------- Renu Raman ARPA:ram@sun.com Sun Microsystems UUCP:{ucbvax,seismo,hplabs}!sun!ram M/S 5-40, 2500 Garcia Avenue, Mt. View, CA 94043