bcase@cup.portal.com (Brian bcase Case) (05/05/89)
>>A couple of years ago there was an article in Byte about a proposed design >>which they called WISC for Writeable Instruction Set Computer. >Honeywell and Buro..whoops UNISYS had mainframes like this, well over >a decade ago. Byte, lives at the cutting edge.... Yes. Such a machine was (is) referred to as a "soft machine." Reading Byte can be hazardous to your health.... The original complaint that "RISC machines use too much memory bandwidth" is where the problem with the whole argument lies. The correct assertion is that "high-performance machines use too much memory bandwidth." That is, RISC or CISC has little to do with it. A high-performance machine will have a good optimizing compiler and its peak instruction rate will be close to, if not at, the clock rate. The compiler will use the simple instructions because that is the best way to cut out cycles. Thus, memory bandwidth is mostly a function of the performance of the system. Soft machine or "WISC" is a bad idea because a truly horizontal microarchitecture is not amenable (enough) to automatic instruction-set customization. Going to a vertical microarchitecture to make the job tractible is called RISC. If the problem of generating horizontal micro- code can be solved, then the best use of it is not soft machines (WISC), but the same a old thing: make the horizontal set *the* instruction set and make the compiler generate code for it directly. The instruction cache will then capture the dynamic behavior of the program. Note that VLIWs and the i860 in dual-instruction mode are like horizontal machines. These architectures will eventually force advanced compilation techniques into the mainstream (years from now), and machine architectures in general might get more horizontal. Or maybe superscalar architectures will take over (note that superscalar both hides and exposes the horizontal microarchitecture at the same time: it will run old, vertical code just fine, but if you arrange things right, you'll get more "horizontalization.").
slackey@bbn.com (Stan Lackey) (05/05/89)
In article <17932@cup.portal.com> bcase@cup.portal.com (Brian bcase Case) writes: >>>A couple of years ago there was an article in Byte about a proposed design >>>which they called WISC for Writeable Instruction Set Computer. > >>Honeywell and Buro..whoops UNISYS had mainframes like this, well over >>a decade ago. Byte, lives at the cutting edge.... > >The original complaint that "RISC machines use too much memory bandwidth" >is where the problem with the whole argument lies. The correct assertion >is that "high-performance machines use too much memory bandwidth." That >Soft machine or "WISC" is a bad idea because a truly horizontal >microarchitecture is not amenable (enough) to automatic instruction-set >customization. Going to a vertical microarchitecture to make the job This is probably true in the general case, but not true for special-purpose. For example, suppose vectors represent a high percentage of the application. Wide-word microcode can prefetch a vector element, increment the address pointer, issue a FP MUL, issue a FP ADD, decr the loop count, and conditionally branch in one cycle, in microcoded vector machines and (I hope) in the generic RISC/VLIW. Clearly, this function will execute many times faster than on a RISC which takes one to two cycles to do each step mentioned above. "WISC" machines would be intended for this kind of application, where the attempt would be to build a general purpose box which is customizable to be cost-effective competing with special-purpose boxes. Clearly, this requires the application to be characterized by spending most of its time in a small set of functions which can be sped up a lot by micro-parallelism, as in the case of a vector instruction set. I know that there is probably no CISC instruction set that makes grep, troff or dhrystone run significantly faster than the fast RISC-based boxes. But that is not where my computing bottlenecks are; mine involve SPICE, logic simulation, fault grading, and stuff like that. -Stan
zeeff@b-tech.ann-arbor.mi.us (Jon Zeeff) (05/08/89)
I don't see that much difference between WISC and a RISC chip and it's cache. In both cases, you are eliminating the external memory accesses necessary to execute some common code sequence. On the WISC chip, you have to set it up explicitly and invoke it with an instruction. On the RISC/cache machine, it's automatic and invoked by the address being reused (meaning that it's going to have to be a subroutine if the code sequence is to be used from many different places in your code). Perhaps we need (or does it already exist) some instructions to control caching. Something like "I'm about to execute some code that I know will be executed alot - keep it in the cache longer than usual" and "don't waste cache space on this - I'm only doing it once". Disclaimer - I just use CPUs. -- Jon Zeeff zeeff@b-tech.ann-arbor.mi.us Ann Arbor, MI sharkey!b-tech!zeeff