mdeale@algol.acs.calpoly.edu (Myron Deale) (06/29/89)
Hello, many thanks to BIT for responding so quickly. The literature on the BIT SPARC is listed as "Advance Information" and dated 6/89. The chip set includes: B5000 Integer Unit, B5100 Floating Point Controller, B5110 Floating Point Chip Set consisting of MPY (/10) and ALU (/20), and B5210 Register File. Notes: presently rated at 80 MHz, ECL 10KH compatible, only need IU (B5000), the other 5 chips make up the floating point subsystem. The MPY and ALU are modified versions of the 3110/20 and are *quite* capable. Power consumption? "If you have to ask ..." [although I've seen worse.] Some thoughts and questions after the first read through: 1) why is LDD listed as taking 2 cycles ? 2) BUSOP is a neat idea though I wonder how useful the present codes are. 3) why would the IU sustain MHOLD (internally) for 2 cycles after release? this slows things up, right? ie. even more than the memory system says. 4) Is MHOLD actv_lo or actv_hi when "asserted" ? I assume actv_lo from looking at the timing diagrams. 5) so, by when does MHOLD have to be inac_hi to avoid wait states ? One minor peeve against BIT, for me, is their timing diagrams. I do fine with AMD and TI, for example, but there are some problem companies. Maybe due to my lack of experience though. 6) only mult step inst. for IU, though "FPU" has integer as well as FP mult (to 64-bit result). 7) delayed control xfer handled nicely, ie. how branches are handled is real keen. 8) When they say "640 MB/s peak bandwidth" that's for the IU only. Then there's the "FPU" which is recommended to have it's own 64-bit data path. I wonder if the 14 Linpack rating accounts for such? 9) Am I reading correctly, there is extended precision (FP) support? 10) Would someone care to explain just how many nano's the low order addresses are early by? My arithmetic says AL is valid around when AH becomes valid. Myron #include <disclaimer.std> // mdeale@cosmos.acs.calpoly.edu // Where are Diogenes' followers today?