[comp.arch] misc arch features requested

colwell@uunet.UUCP (Robert Colwell) (03/29/88)

We built in to the TRACE VLIW a facility that we call the PCQ, short
for Program Counter Queue.  This set of about 20 MSI chips and RAMs
can collect 2K PC values.  The user of this facility can control the
start and stop criteria, such as starting collection on a given PC
value and waiting N clocks afterwards before shutting down the PCQ.
Other scanloop tools then dump the contents for analysis.  We also
provided this hardware with the ability to trap the CPU when half
full.  The trap handler then knows to dump the PCQ before allowing
that user process to continue -- this mode is very useful for program
tracing, instruction cache modelling and experimentation, and linker
tweaking.  There's lots more to it, but perhaps you get the idea.

I am writing a paper describing this facility, but I'm having some
trouble placing it in its proper context.  In other words, what similar
facilities have other manufacturers provided (and reported on)?  I've
heard, for instance, that the VAXes have a bus monitor built into the
SBI such that the last N transfers are available for diagnosis.  But
I've not seen this reported in print.  Cargill and Locanthi's ASPLOS-II
paper is in the same spirit, but what we've provided is so far beyond
what they're suggesting it's almost funny.  Does anyone have references
that would help?  Thanks a lot.

Bob Colwell            mfci!colwell@uunet.uucp
Multiflow Computer
175 N. Main St.
Branford, CT 06405     203-488-6090