mark@mips.COM (Mark G. Johnson) (04/26/89)
In article <100524@sun.Eng.Sun.COM>, dgh%dgh@Sun.COM (David Hough) writes: > I have heard that adder carry propagate time and multiplier array > size are the key constraints with a floating-point chip; .... Well, only true for those chips which don't have an explicit hardware divide unit, e.g. Clipper, Intel 860, TI 8847, Moto 88K, Transputer. These folks use the multiply and the add hardware, plus a Newton-Rhapson iterative algorithm, to synthesize division. Other FP chips have a separate functional unit for divides (allowing a divide to be overlapped with a multiply & an add). I believe HP Precision, Weitek, and MIPS have FP chips with divider hardware. The divider can indeed become the critical path of the FP unit. > ... Memory bandwidth tends to > be the key constraint on overall system performance unless > floating-point division and sqrt dominate. The last describes > a minority of programs but they are quite important in some > influential circles. As David has said before on this forum, the circuit simulator SPICE executes a very large number of divides and square roots. To VLSI designers (like the ones who design FP chips!), SPICE is quite an important program. Hint: look at the equations for the pinchoff voltage of a field effect transistor (such as the MOSFETs in CMOS technology). Count the number of divides and square roots. -- -- Mark Johnson MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086 ...!decwrl!mips!mark (408) 991-0208
roger@wraxall.inmos.co.uk (Roger Shepherd) (04/28/89)
In article <18106@obiwan.mips.COM> mark@mips.COM (Mark G. Johnson) writes: >In article <100524@sun.Eng.Sun.COM>, dgh%dgh@Sun.COM (David Hough) writes: > > I have heard that adder carry propagate time and multiplier array > > size are the key constraints with a floating-point chip; .... >Well, only true for those chips which don't have an explicit hardware >divide unit, e.g. Clipper, Intel 860, TI 8847, Moto 88K, Transputer. ^^^^^^^^^^^ >These folks use the multiply and the add hardware, plus a Newton-Rhapson >iterative algorithm, to synthesize division. Can I correct this. The T800 transputer does not have a multiplier or divider as such. Both operations are performed iteratively, the multiplication generating 3 bits of product per cycle, the divider generating 2 bits of quotient per cycle. I should point out that the T800 FPU was designed to fit into a very small area (about 20 sq mm); the T800 was announced in 1987 and it contains an integer processor, 4 communication links and 4k bytes of on-chip RAM. At the time the die (about 1 sq cm) was the largest we could contemplate manufacturing - it was die size as much as anything which determined the implementation; large array multipliers were out. Roger Shepherd, INMOS Ltd JANET: roger@uk.co.inmos 1000 Aztec West UUCP: ukc!inmos!roger Almondsbury or uunet!inmos-c!roger Bristol BS12 4SQ INTERNET: @col.hp.com:roger@inmos-c