webber@porthos.rutgers.edu (Bob Webber) (06/24/88)
In article <270@laic.UUCP>, darin@nova.laic.uucp (Darin Johnson) writes: >... > The biggest drawback I can see, is that there would have to be 'optimizing > assemblers'. Of course, such an assembler would find it difficult to > take advantage of some common RISC idioms, such as register windows. Actually there is a -O optimize option on all the Sun assemblers (for span dependent jumps and such), but with the Sun 4 (SPARC chip) it now takes a numeric option for level of peephole optimization (apparently meant to be backend for compiler-generated assembler). ----- BOB (webber@athos.rutgers.edu ; rutgers!athos.rutgers.edu!webber)