mshute@r4.uucp (Malcolm Shute) (03/15/90)
In article <8332@hubcap.clemson.edu> billo@nova.npac.syr.edu (Bill O) writes: >[about indirect addressing on SIMD] Can I ask the net for some clarification on some of the points which he makes, (especially wrt the most useful interpretation of Flynn's notation). >SIMD implies that every processor must be doing the same thing at the >same time, and that usually means addressing the same data at the same >time. Though, if I say to every processor "copy contents of i-th cell to the 4th cell" (where the value in 'i' is different on each machine), then I am indeed making them do the same thing at the same time. * I note, however, your use of the words "usually means" to indicate what tends to happen in most practical implementations to date. * I have assumed that by the words "same data" you mean "same address", since being siMD, it must have access to multiple data streams. > In terms of implementation, SIMD machines typically have bit >serial processors which are partitioned into small groups to share >memory chips and the like. Only one address is presented to each >memory chip, which produces a word full of data, which is then split >off into individual bits for each processor in the associated group. >Thus there is no opportunity for each processor to provide its >own address. Right, this is where I really question the value of this interpretation of Flynn's notation. What you have described seems to me to be a description of any SISD machine which can be implemented using bitslicing. There's nothing wrong in that, of course. My question to the net is, however, what is the value of the classification scheme if we can lump all bitwise-parallel von Neumann computers into the SIMD slot. Viewed the other way, if all of the processors access memory addresses in strict harmony like this, then they are only biting off parts of the *same* data stream. (And hence all qualify as being SISD). Surely, it is only the MAMD machines which you mentioned later which can claim to qualify as true SIMD. Just a thought. Malcolm SHUTE. (The AM Mollusc: v_@_ ) Disclaimer: all
pfeiffer@nmsu.edu (Joe Pfeiffer) (03/17/90)
mshute@r4.uucp (Malcolm Shute), in <8332@hubcap.clemson.edu>: | |In article <8332@hubcap.clemson.edu> billo@nova.npac.syr.edu (Bill O) writes: |>[about indirect addressing on SIMD] | |> In terms of implementation, SIMD machines typically have bit |>serial processors which are partitioned into small groups to share |>memory chips and the like. Only one address is presented to each |>memory chip, which produces a word full of data, which is then split |>off into individual bits for each processor in the associated group. |>Thus there is no opportunity for each processor to provide its |>own address. | |Right, this is where I really question the value of this interpretation |of Flynn's notation. | |What you have described seems to me to be a description of any SISD |machine which can be implemented using bitslicing. There's nothing |wrong in that, of course. My question to the net is, however, what is |the value of the classification scheme if we can lump all bitwise-parallel |von Neumann computers into the SIMD slot. | |Viewed the other way, if all of the processors access memory addresses |in strict harmony like this, then they are only biting off parts of |the *same* data stream. (And hence all qualify as being SISD). |Surely, it is only the MAMD machines which you mentioned later |which can claim to qualify as true SIMD. Of course, you're right. This is similar to the reason that one of my favorite questions at oral exams is ``argue that a single-CPU Cray-1 is an example of each of Flynn's categories.'' We generally interpret the bits making up a single word as a single scalar value, making a von Neumann engine SISD instead of SIMD. The bits in a bit plane, however, we interpret as elements of a matrix, so MPP is SIMD, not SISD. This is also consistent with the common placement of the scalars making up a matrix; each scalar is spread across several planes within a single PE. It is also possible to argue the MPP (for example) is MIMD, due to the Mask bit; or even MISD because of asynchronous IO. None of these are particularly useful arguments to make, however, because ``SIMD'' best captures the flavor of the machine. -Joe.
gerry@zds-ux.UUCP (Gerry Gleason) (03/17/90)
In article <1080@m1.cs.man.ac.uk> mshute@r4.UUCP (Malcolm Shute) writes: |What you have described seems to me to be a description of any SISD |machine which can be implemented using bitslicing. There's nothing |wrong in that, of course. My question to the net is, however, what is |the value of the classification scheme if we can lump all bitwise-parallel |von Neumann computers into the SIMD slot. |Viewed the other way, if all of the processors access memory addresses |in strict harmony like this, then they are only biting off parts of |the *same* data stream. (And hence all qualify as being SISD). |Surely, it is only the MAMD machines which you mentioned later |which can claim to qualify as true SIMD. If I understand you correctly, you are missing an important part of (at least some) SIMD architectures. Take TMI's connection machine; it has and interconnection network that can permute a word from each processor to any other processor in a constant amount of time (well, not quite, there is a factor of log2(number of PE's) in the equation, but constant for a given machine size). This network is a very important part of the computational capacity of the machine. Gerry Gleason