brooks@lll-crg.llnl.gov (Eugene D. Brooks III) (04/18/88)
Now that the super duper high performance RISC chip sets are being dumped upon us (I guess dumped is poor word, as we are eagerly awaiting them), some with seperate single chip code and data caches, can anyone provide some information on what type of cache control mechanisms these processor architectures provide? In bus based shared memory multiprocessors one can have cache coherence managed with good efficiency, but modest numbers of the latest hotrods seem to be quite capable of saturating any reasonable bus even with coherent copy/back caches. One eventually will want to move on to "non bus" shared memory subsystems where setting up an automatic cache coherence scheme is far more difficult. Using software cache control, where loads and stores are generalized with several cache options attached to each, for instance "plain load (from cache if its there)", "load replacing the cache line with a fresh line from memory", ...; "store (only in cache if its there)", "store writing through the cache to main memory leaving the value in cache", "store writing though the cache to main memory, dumping the line", etc ,etc. Such custom cache operations look a lot like register management, and I am quite a proponent for forgetting the cache, having LOTS of registers, and pipelining all memory accesses. Anyway, as long as the processors have a limited register file we will need the cache, and we need to have some way of managing the cache with an intellegent compiler. So what type of cache control is supported by the new micros?
walter@garth.UUCP (Walter Bays) (04/19/88)
In article <6258@lll-winken.llnl.gov> brooks@lll-crg.llnl.gov (Eugene D. Brooks III) writes: >Now that the super duper high performance RISC chip sets are being dumped >upon us (I guess dumped is poor word, as we are eagerly awaiting them), >some with seperate single chip code and data caches, can anyone >provide some information on what type of cache control mechanisms these >processor architectures provide? In bus based shared memory multiprocessors >one can have cache coherence managed with good efficiency, but modest numbers >of the latest hotrods seem to be quite capable of saturating any reasonable >bus even with coherent copy/back caches. The Clipper supports non-cached, write-through, and copy-back modes per virtual memory page. They are set by writing the CAMMU (cache and memory management unit) control register. (The I-CAMMU performs instruction pre-fetch, so the instruction hit rate is very high.) Under CLIX (UN*X System V) the three cache modes can be specified by ld(1) per text, data, and stack segments. Default mode is copy-back. For very large programs with poor locality of reference, write-through can actually be a bit faster for the data segment. Depending on reference patterns, you might want to use write-through for multi-processors. The bus would saturate with more than a few Clippers, and that gets to the conjecture in your note. Non-bus architectures may be needed for very fast multi-processors. Many RISC processors expose the pipeline for compiler control. Are there any processors that expose the cache for compiler control, and would that be useful for hypercubes? -- ------------------------------------------------------------------------------ Any similarities between my opinions and those of the person who signs my paychecks is purely coincidental. E-Mail route: ...!pyramid!garth!walter USPS: Intergraph APD, 2400 Geng Road, Palo Alto, California 94303 Phone: (415) 852-2384 ------------------------------------------------------------------------------