jse@hprnd.HP.COM (Jeff Ebeling) (08/21/90)
Does anyone out on the net have any information as to specific architectures and I/O card / driver interactions for VME interfaces? Specifically what I am interested in are the following questions: 1) Are there any cards out there, other than processor cards, that use the RMW operation on the VME bus? If so what are they, and why do they need it? 2) Are there any VME cards out there that have asynchronously writeable card and processor data structures that may exist within a single cache line? That is can the card have a byte or word that it can write asynchronously, in the same line as a byte or word that the host can write asynchronously? This would require that processors with data cache be forced never to cache that line. 3) What is the smallest unit that most cards write to in memory space. The VME spec allows writes down to the byte level, but do many I/O cards use this capability? If so, in what application and why? 4) Of the VME processor cards that have a data cache, do their cache / memory management architectures allow for uncacheable memory locations? Is this feature available in increments smaller than a page? 5) I assume third party card drivers are usually written to run on the 680x0 series of processors. I also assume there are probably a number of drivers written for SPARC, Intel x86s, Motorola 88000s etc.. What is usually done in terms of driver porting? Specifically, how is the transition from a processor w/o a data cache to a processor with a data cache usually handled? Who does the ports? 6) Are drivers usually written with a single I/O card controlled by a single processor paradigm in mind, or are they written to allow multiple processors to control a single card? Answers to any of the above questions would be greatly appreciated. Jeff jse@hprnd.hp.com Hewlett Packard Roseville Networks Division