crayfe@nas.nasa.gov (Cray Hardware Support) (03/05/91)
I n article 18983: >From: rmbult01@ulkyvx.bitnet (Robert M. Bultman) >The CDC 6600, 7600, STAR 100, and IBM 360/195 made use of an >instruction stack. The implementation varied, but generally they were >used to speed up operation of loops. > 1) Do any recent (> 1985) machines use this, or has this been > obviated by the use of cache? All of the Cray machines use instruction stacks to reduce unnecessary references to memory. It is hardware controlled and the adress of the next instruction to issue and jump addresses were checked to see if they fell in the stack. > 2) Was this mechanism software controllable, or was it a > hardware-only mechanism? (The reference (see below) regarding > this indicated it was hardware only using an address comparison > to determine if the backwards jump fell within the limit of the > instruction stack. This sounds like a very small i-cache but > is contained within the CPU.) It is basically a small i-cache. On the cray-2 it comprised 256 64 bit words. Can't remember off the top of my head what it is on the Y-MP. > 3) Would such a mechanism help RISCs? (Why? Why not?) Sorry, don't know much about RISCs. YYYY PPPP Y Y P P Y Y P P YY YMMMMMMMMMP PP YYYY PPPP Y P Y P Y P Buy Crays! Support underworked Y P overpaid field engineers. Y P YMMMMMMMMMP Gordon Foster crayfe@wil.nas.nasa.gov