[comp.arch] Query: memory architecture for high-speed random access

reuven@isgtec.UUCP (Reuven Soraya) (03/01/90)

In "Contrasting Architectures of Minisupercomputers: Form Shapes Function"
in Supercomputing Review (1st issue) it is observed that:

	"[...] the Convex, Cydrome and Multiflow minsupers architectures
	have no cache at all.  They rely instead upon more intensive inter-
	leaving. That makes the C-series and Trace computers more suitable
	for problems with large amounts of random data."

This suprises me and I would like to get more information about (a) these
machines and (b) this concept in general.

Thanks!

Reuven S.