grunwald@uiucdcsm.cs.uiuc.edu (06/27/88)
So, Electronic News and some other rag had articles on the P7 (aka gemini) project at Intel, and the formation of BiiN (right name?), a jointly owned Siemans and Intel company. Any news about this? Speculations? I'll start the ball rolling: why do the articles mention iSC, the people that make the iPSC/2? Admittedly, the article said that iSC would *not* be a Biin group; however, the Siemans effort is towards fault tolerent computing, using multiprocessor systems. This would seem to coincide with the charter of iSC. Also, what's the group going to produce? If the latest Intel RISC ``micro controller'' is an early spin-off, what else are they planning on releasing? How can RISC & the 432 group coincide?
mslater@cup.portal.com (06/29/88)
>So, Electronic News and some other rag had articles on the P7 (aka gemini) >project at Intel, and the formation of BiiN (right name?), a jointly >owned Siemans and Intel company. > >Any news about this? Speculations? My guess is that BiiN is going to use an implementation of the 80960 archi- tecture, whose initial implementation is now being sold as an embedded control processor. I suspect the BiiN version will have multiple instruction pipelines and other goodies to greatly increase performance over the existing 7.5 MIPS chips. As for RISC and the 432, I think it's something like this. Build a RISC machine with a load/store architecture, single-cycle instructions, lots of pipelining, a big register set, etc. Then add microcode support for complex data type and complex instructions, and also for concurrency support and task switching. You can stick to the RISC instructions and run as fast as a pure RISC machine, or use the complex instructions if they're useful to you. Now the RISC purists I'm sure would argue that all this complex stuff can't help but slow down the basic instruction set. But it might be worth it. Michael Slater, Editor and Publisher, Microprocessor Report mslater@cup.portal.com sun!portal!cup.portal.com!mslater 415/494-2677
aglew@urbsdc.UUCP (07/01/88)
>How can RISC & the 432 group coincide?
A while back the history of the 432 and '960 was
described in this group. As I understand, the group
that did the 432 was enlightened by this experience,
and took a swing the other way.andrew@frip.gwd.tek.com (Andrew Klossner) (07/15/88)
[]
"As for RISC and the 432, I think it's something like this.
Build a RISC machine with a load/store architecture,
single-cycle instructions, lots of pipelining, a big register
set, etc. Then add microcode support for complex data type and
complex instructions, and also for concurrency support and task
switching. You can stick to the RISC instructions and run as
fast as a pure RISC machine, or use the complex instructions if
they're useful to you."
Hillsboro scuttlebutt has it that the 80960 has all the object-oriented
and silicon operating system cruft of the 432, but if all you document
are the RISCy instructions, you can call it a RISC.
From a market viewpoint, if it does what it's documented to do, it does
it fast, and it's cheap, it really doesn't matter what's inside.
-=- Andrew Klossner (decvax!tektronix!tekecs!andrew) [UUCP]
(andrew%tekecs.tek.com@relay.cs.net) [ARPA]