arnold@geac.UUCP (10/22/87)
I have been hearing a lot about this new Reduced Instruction Set C? technology...well I understand that if you restrict yourself to a small instruction set and run it fast you get faster compiled programs (I guessed this was the assumption). But I have been unable to find out just what the hardware differance is (though I have heard referance to arrays?(I think that was it)). So could someone out there explain a bit? thanx
collier@charon.unm.edu (Uncia Uncia) (10/25/87)
i would be grateful if someone could provide a quicky review of the MIPS pipeline. i have forgotten the details but if i remember correctly it was very simple and elegant, so perhaps it wouldn't take up too much of someone's time. -- Michael Collier University of New Mexico Computing Center 2701 Campus Blvd. Albuquerque, NM 87131 ...!ihnp4!lanl!\ unm-la!unmvax!charon!collier ...!cmcl2!beta!/
mash@mips.UUCP (John Mashey) (11/02/87)
In article <1656@geac.UUCP> arnold@geac.UUCP writes: >I have been hearing a lot about this new Reduced Instruction Set C? >technology...well I understand that if you restrict yourself to a >small instruction set and run it fast you get faster compiled >programs (I guessed this was the assumption). But I have been unable >to find out just what the hardware differance is (though I have >heard referance to arrays?(I think that was it)). >So could someone out there explain a bit? Well, it's not really new [Seymour Cray has been designing RISCy machines for eons, the IBM 801 is well over 10 years old, and various folks (Pyramid, Ridge) have been selling RISC machines for a while.] The only really recent part is doing it in VLSI, and the ramifications thereof. There have been many discussions in this newsgroup, so rather than repeating them, how about just a few good references: 1) John Hennessy, "VLSI Processor Architecture", IEEE Trans on Computers, C-33, no 12, Dec 1984, 1221-1246. 2) David A. Paterson, "Reduced Instruction Set Computers", Comm. ACM 28, 1 (Jan 1985), 8-21. 3) George Radin, "The 801 Minicomputer", ACM SIGARCH 10, 2 (March 1982). -- -john mashey DISCLAIMER: <generic disclaimer, I speak for me only, etc> UUCP: {ames,decwrl.prls,pyramid}!mips!mash OR mash@mips.com DDD: 408-991-0253 or 408-720-1700, x253 USPS: MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086
mash@mips.UUCP (John Mashey) (11/02/87)
In article <1710@charon.unm.edu> collier@charon.UUCP (Uncia Uncia) writes: >i would be grateful if someone could provide a quicky review >of the MIPS pipeline. i have forgotten the details but if i >remember correctly it was very simple and elegant, so perhaps >it wouldn't take up too much of someone's time. See Moussouris, et al, "A CMOS RISC Processor with Integrated System Functions", Proc IEEE COMPCON, SanFrancsico, March 1986, 126-143, for the details. The integer unit is basically a 5-stage pipe: I-cache reference (instruction fetch) Register Fetch / Decode / next PC determination ALU / Address calculate Data-cache / memory access Write-back to register file IF RD ALU MEM WB IF RD ALU MEM WB IF RD ALU MEM WB IF RD ALU MEM WB IF RD ALU MEM WB This is a simplification: some things happen on half-cycle boundaries, and virtual-physical translations are also happening in an overlapped fashion. -- -john mashey DISCLAIMER: <generic disclaimer, I speak for me only, etc> UUCP: {ames,decwrl.prls,pyramid}!mips!mash OR mash@mips.com DDD: 408-991-0253 or 408-720-1700, x253 USPS: MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086
colwell@mfci.UUCP (Robert Colwell) (11/11/87)
>Well, it's not really new [Seymour Cray has been designing RISCy machines >for eons, the IBM 801 is well over 10 years old, and various folks >(Pyramid, Ridge) have been selling RISC machines for a while.] The only >really recent part is doing it in VLSI, and the ramifications thereof. >There have been many discussions in this newsgroup, so rather than repeating >them, how about just a few good references: > >1) John Hennessy, "VLSI Processor Architecture", IEEE Trans on Computers, >C-33, no 12, Dec 1984, 1221-1246. > >2) David A. Paterson, "Reduced Instruction Set Computers", Comm. ACM 28, >1 (Jan 1985), 8-21. > >3) George Radin, "The 801 Minicomputer", ACM SIGARCH 10, 2 (March 1982). >-- >-john mashey DISCLAIMER: <generic disclaimer, I speak for me only, etc> >UUCP: {ames,decwrl.prls,pyramid}!mips!mash OR mash@mips.com >DDD: 408-991-0253 or 408-720-1700, x253 >USPS: MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086 But please keep in mind that there is still room for other opinions here...I see almost nothing RISCy about Pyramid or Ridge. Pyramid seemed like a RISC to the novice because it had lots of registers organized in windows, which was like RISC-I, and RISC-I is a RISC, so Pyramid must be too? No way, unless you think the IBM 801 was not. By the way, all three of the above papers were reprinted in Stallings' recent 'Reduced Instruction Set Computers', IEEE catalog EH0251-9. I notice that nobody has taken up Wirth's challenge at the ASPLOS-II conference concerning the dangers inherent in the current approach of "performance above all else". He mentioned items like undetected integer overflows and broken floating point processing as being the norm. I bet he knows this, but he didn't mention it. The problem is that when you've got several streams of floating point operations in the air at the same time, you could have a royal mess if any one of them takes an exception AND you have to handle it a la IEEE. One way out is to have the exceptions be flagged in a sticky register, and check that register at the completion of the computations; if clean, you win. If you do the flops sequentially, you can tell the user exactly what went wrong and where, but it won't help -- you won't have any users, because they'll have bought someone else's machine. -- Bob Colwell {yale!mfci!colwell} {203-488-6090} -- (pretend there's a standard generic disclaimer here)
mash@mips.UUCP (11/12/87)
In article <197@m2.mfci.UUCP> colwell@m6.UUCP (Robert Colwell) writes: >here...I see almost nothing RISCy about Pyramid or Ridge. Pyramid >seemed like a RISC to the novice because it had lots of registers >organized in windows, which was like RISC-I, and RISC-I is a RISC, >so Pyramid must be too? No way, unless you think the IBM 801 was >not. Pyramid RISCyness has been debated before in this newsgroup; personally, it seems like being on the CISCy edge of RISC to me, or RISCy edge of CISC, but it didn't seem reasonable not to mention it. Also, somebody from Celerity complained (probably fairly) on not being included in the list. What's un-RISCy about RIDGE? (allowing non-VLSI designs to be RISC) In any case, this wasn't supposed to be a definitive list, or detailed analysis, or any such thing, especially since we all know there's no such thing as a sharp boundary between RISC and CISC anyway. Certainly, the 801 is on the RISCy side of all this. >I notice that nobody has taken up Wirth's challenge at the ASPLOS-II... >integer overflows and broken floating point processing as being the >norm. I bet he knows this, but he didn't mention it. The >problem is that when you've got several streams of floating point >operations in the air at the same time, you could have a royal mess >if any one of them takes an exception AND you have to handle it a la >IEEE. One way out is to have the exceptions be flagged in a sticky >register, and check that register at the completion of the >computations; if clean, you win. Just out of curiosity, what DOES Multiflow do on this? One of your OS folks gave a good talk in my session at USENIX, but I don't recall how the IEEE-exception-handling was done. -- -john mashey DISCLAIMER: <generic disclaimer, I speak for me only, etc> UUCP: {ames,decwrl,prls,pyramid}!mips!mash OR mash@mips.com DDD: 408-991-0253 or 408-720-1700, x253 USPS: MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086
krish@weitek.UUCP (Krishnan Sridhar) (08/27/88)
Several articles have been posted in this group in the recent past comparing
the performance of certain benchmarks on different types of machines, most
notably RISC machines.
Just what EXACTLY is RISC? I know it's an acronym for Reduced Instruction Set
Computer i.e., the intruction set is a lot simpler and smaller and therefore,
can be executed directly in hardware much faster. I am also aware of the
concept of register file windows (from RISC II - was it GOLD or BLUE or
neither?). Apart from these two concepts, are there any others unique to RISC
architecture? Frequently, I hear the term "Load-Store Architecture" applied
specifically to RISC machines. What *exactly* does it mean and what are it's
implications in the architecture of a machine?
Much has been talked about RISC in the past year or so, with the introdution
of RISC processors from SUN, MIPS, MOTOROLA etc. Is the concept of RISC really
that revolutionary, or is it just another infinitesimal addition to the list
of buzzwords already floating around?
Please note that I am not trying to critique RISC architecture in any way. My
exposure to RISC is limited and I would really appreciate getting responses to
my questions from people out there in the arch.comp land.
Thanks much in advance.
P.S. Also a list of references and/or books on RISC will be appreciated.
My apologies, if this topic has already been beaten to death; I am
fairly new to this net.