zs01+@andrew.cmu.edu (Zalman Stern) (02/25/90)
[In an ancient message, Brian Case points out that Bill Wulf's WM machine can achieve the performance of a vector machine on vectorizeable codes. Dan Hendrickson asks if this machine has ever been implemented and points out that there are many paper designs which have not made it to silicon due to the difficulty of implementing them.] So far as I know, the WM architecture has not yet made it into real silicon. The essential feature of WM that gives it excellent performance on vectorizable problems is the use of implicit loads. This is a technique where one sets up a register to do a load or store everytime it is accessed. The addresses used are "vector" addresses in the sense that they have a constant stride. This technique is used in iWarp, a long instruction word processor done by by people at Carnegie Mellon and Intel. Two articles on this processor are: Borkar, S., Cohn, R., Cox, G., Gleason, S., Gross, t., Kung, H. T., Lam, M., Moore, B., Peterson, C., Pieper, J., Rankin, L., Tseng, P. S., Sutton, J., Urbanski, J., and Webb, J. "iWarp: An Integrated Solution to High-Speed Parallel Computing." In: Proceedings of Supercomputing '88, IEEE Computer Society and ACM SIGARCH. 1988 Cohn, R., Gross, T., Lam, M., and Tseng, P.s. "Architecture and Compiler Tradeoffs for a Long Instruction Word Microprocessor." In: Proc. Third SIGARCH/SIGPLAN Symposium on Architectural Support for Programming Languages and Operating Systems, ACM, Boston, 1989, pp. 1-14. Implicit register operations are just one way of getting good performance on vectorizeable code without having special vector instructions. Superscalar and Very Long Instruction Word (VLIW) machines also do well in this arena. One can look at the IBM RS/6000 or the Intel i960 for superscalar and the Multiflow Trace machines for VLIW. Sincerely, Zalman Stern Internet: zs01+@andrew.cmu.edu Usenet: I'm soooo confused... Information Technology Center, Carnegie Mellon, Pittsburgh, PA 15213-3890