[..] comp.lsi

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net.lsi is being renamed comp.lsi (0 replies, 11/07/86)

Looking for Andreas Nowatzyk (1 reply, 11/15/86)

Who to contact at Chip making places? (0 replies, 11/19/86)

How does one synthesize oddball waveforms? (0 replies, 12/07/86)

Info-VLSI mailing list request (0 replies, 12/09/86)

DRAM senseamp waveform (0 replies, 12/09/86)

Path to mosis? (0 replies, 12/14/86)

espresso (1 reply, 12/16/86)

Magic under X on the HP 9000/320 (0 replies, 12/17/86)

Magic under X? (0 replies, 12/17/86)

Automatic standard cell layout software (0 replies, 12/18/86)

cifplot, sun3's, and pen plotters (0 replies, 12/19/86)

how does layout affect threshold matching? (1 reply, 12/26/86)

Spice models request (1 reply, 12/31/86)

I missed a Magic bug fix, could someone help ? (0 replies, 01/08/87)

Magic resistance bug fix (0 replies, 01/09/87)

Magic bug fix (0 replies, 01/09/87)

Problems with magic reading scmos labels (1 reply, 01/21/87)

Crippling SPICE Level 2 bug in VMAX param (0 replies, 01/22/87)

WANTED: lsi design tools (0 replies, 01/29/87)

IEEE VLSI Workshop (0 replies, 01/30/87)

MIT VLSI tools (0 replies, 01/31/87)

Where to get rsim? (2 replies, 02/01/87)

caesar for suns (0 replies, 02/02/87)

info-vlsi mailing list problem (0 replies, 02/03/87)

Question about spice 3 (0 replies, 02/05/87)

Statistics on spice 2 and spice 3. (0 replies, 02/05/87)

Magic on a Sun 110? (4 replies, 02/06/87)

CALL FOR PAPERS - PARALLEL PROCESSING FOR CAD APPLICATIONS (0 replies, 02/11/87)

compiling Magic on a SUN3 --- problem with Rect structures (0 replies, 02/13/87)

Graphics Immage or Pattern recognition VLSI (2 replies, 02/13/87)

Mpanda templates anyone? (1 reply, 02/15/87)

Long Postings (0 replies, 02/20/87)

Magic Technology File for MOSIS' technology - CBPE 3U (0 replies, 02/24/87)

4.2 CAESAR (0 replies, 02/25/87)

Looking for TI TMS5501 or replacement (0 replies, 03/03/87)

Toshiba voice recognition chip (1 reply, 03/16/87)

uP Figure of Merit (0 replies, 03/18/87)

ext2sim for the latest rsim (0 replies, 03/19/87)

Josephson Junction computers (10 replies, 03/23/87)

Magic to PostScript plotting (0 replies, 03/24/87)

Valid libraries. (0 replies, 03/25/87)

Workshop Graphics Hardware (0 replies, 03/30/87)

SPICE 2G6 Bugs ? (0 replies, 04/09/87)

SIM2SPICE BUG + FIX. (0 replies, 04/10/87)

Info-VLSI trouble (0 replies, 04/10/87)

A workaround for "Internal timestep error" (0 replies, 04/11/87)

Internal time step error in SPICE2G6 ? (3 replies, 04/13/87)

SPICE time step too small (0 replies, 04/13/87)

SPICE Internal time step to small (0 replies, 04/14/87)

SPICE time-step too small (3 replies, 04/17/87)

SPICE2 Timestep too small errors (0 replies, 04/22/87)

AED display on a Sun system (0 replies, 04/22/87)

mpla and new mosis rules (1 reply, 04/24/87)

RSIM with MAGIC (0 replies, 04/24/87)

SPLICE compilation problems (0 replies, 04/24/87)

mextra (0 replies, 04/24/87)

Request: Real World SPICE input files (0 replies, 04/25/87)

CIF file format (3 replies, 04/27/87)

extension of mextra (0 replies, 04/27/87)

changes made to scmos.tech (0 replies, 04/28/87)

self-checking circuits (0 replies, 04/28/87)

Drawing tool (0 replies, 04/28/87)

Anyone using SECS? (0 replies, 05/02/87)

PLease add to Si compiler users' group (0 replies, 05/04/87)

Silicon Compiler Users Group (0 replies, 05/04/87)

magic tech file for the MOSIS 3u CBPM (0 replies, 05/12/87)

magic and the AED767 (0 replies, 05/12/87)

need RTL and/or ISP software (0 replies, 05/12/87)

Newsgroup for the topic of Silicon Compilers (0 replies, 05/15/87)

Magic driver for Vectrix? (0 replies, 05/15/87)

ASIC vendor survey (0 replies, 05/16/87)

EDIF Version 2 0 0 (0 replies, 05/17/87)

Si Compilers (0 replies, 05/19/87)

CIF to PostScript? Magic to PostScript? (0 replies, 05/19/87)

silicon compilers (1 reply, 05/19/87)

What on earth is EDIF?? (0 replies, 05/19/87)

EDIF V 2 0 0 grammar (0 replies, 05/19/87)

Newsgroup for silicon compilers (3 replies, 05/20/87)

Wanted magic driver (0 replies, 05/20/87)

CMOS power estimators? (0 replies, 05/26/87)

SUN3 graphics driver for MAGIC 4.0 (0 replies, 05/26/87)

Available (3 replies, 05/26/87)

Need help in porting Magic (0 replies, 06/01/87)

silicon-compilers users group (0 replies, 06/03/87)

silicon-compilers (0 replies, 06/03/87)

HPUX Magic + X Colors Problem. (0 replies, 06/04/87)

Experience with VLSI tool ports to 3B, Sys. V? (0 replies, 06/10/87)

Info-VLSI (2 replies, 06/18/87)

Wanted: info on porting Berkeley VLSI CAD to Encore & Sequent (0 replies, 06/19/87)

Looking for a process fabrication engineer (0 replies, 06/19/87)

Database conversion (0 replies, 06/24/87)

VLSI Journals and magazines (0 replies, 06/25/87)

Modelling interconnect (1 reply, 06/26/87)

Info needed (1 reply, 06/29/87)

Interconnect modelling (0 replies, 06/30/87)

MOSIS scalable cmos (0 replies, 07/01/87)

Wanted: Silicon Compiler information (0 replies, 07/02/87)

Ford EEC-IV & Intel 8096 (3 replies, 07/03/87)

SPICE / floating-point benchmarks (0 replies, 07/04/87)

SPICE benchmarks: measurements (0 replies, 07/04/87)

MFB Hardcopy? (0 replies, 07/08/87)

wanted: spice description (0 replies, 07/14/87)

EDIF dial-up BBS (0 replies, 07/15/87)

Spice Benchmark Models (1 reply, 07/19/87)

Wanted -- Caesar to Magic Translator (1 reply, 07/19/87)

Public Domain Software. (0 replies, 07/23/87)

SPICE Benchmarks on FPS machines. (0 replies, 07/23/87)

Change of Address (0 replies, 08/02/87)

Magic on Unix V.3 ?? (0 replies, 08/04/87)

A Definition of Silicon Compilation (3 replies, 08/05/87)

Radiation effects on semiconductors (4 replies, 08/07/87)

Wanted Berkeley PLA to EDIF translator (0 replies, 08/15/87)

Intel quote on 386 Multiply bug (0 replies, 08/17/87)

Spice2G6 on HP9000 HPUX (0 replies, 08/19/87)

Postscript output from Magic (1 reply, 08/20/87)

RAM design for MAGIC SCMOS? (0 replies, 08/20/87)

address change for cif to postscript translator (0 replies, 08/24/87)

80386 Multiply: quote from Intel (3 replies, 08/26/87)

Path to UC Santa Barbara (0 replies, 08/27/87)

ASPLOS-II ADVANCE PROGRAM (0 replies, 08/29/87)

Please removing me from this mailing list. (0 replies, 08/29/87)

kiss.1 man page (0 replies, 09/02/87)

Crystal and Spice difficulties (1 reply, 09/04/87)

has anyone tried SCALP? (0 replies, 09/04/87)

Spice Parameters (2 replies, 09/09/87)

VLSI tools on Mac-2's? (2 replies, 09/09/87)

Magic tech file is out-of-date (0 replies, 09/10/87)

spice3b1 vs. spice3a7 (0 replies, 09/11/87)

SPICE3B1 (6 replies, 09/11/87)

MOSIS Spice parameters (1 reply, 09/14/87)

Benchmark results using SPICE (0 replies, 09/15/87)

SPICE benchmark input files (0 replies, 09/15/87)

LOOKING FOR SOFTWARE COMSIDERING EMI (1 reply, 09/17/87)

SPICE parameters from the MOSIS Service (0 replies, 09/21/87)

Soft error rates in DRAM (0 replies, 09/22/87)

BUGs in spice 3a7 & 3b1 (0 replies, 09/22/87)

Looking for PD EDIF parser (0 replies, 09/23/87)

C version of SPICE wanted (0 replies, 09/25/87)

Soft Error rates in dynamic RAM (0 replies, 09/25/87)

VLSI implementation of ECC (1 reply, 09/27/87)

The 18th Int'l Sym. on Fault-Tolerant Computing (0 replies, 09/29/87)

Question: cifplots on laser printers? (0 replies, 09/30/87)

SPICE3 ON SUN (0 replies, 10/05/87)

KIC on SUN (0 replies, 10/06/87)

Behavioral Silicon Compiler Thesis Available (0 replies, 10/07/87)

Logic Synthesis Software. (0 replies, 10/07/87)

PD circuit extractor (0 replies, 10/08/87)

Magic on Sun 3s (0 replies, 10/14/87)

Request for info on plotters (0 replies, 10/21/87)

Modeling the Skin effect (0 replies, 10/22/87)

Bug fixes on spice3b1 (0 replies, 10/22/87)

Magic on Sun 3/110c's (0 replies, 10/23/87)

Help needed when using DBX and MAGIC (4 replies, 10/23/87)

Info on circuit simulators wanted (0 replies, 10/24/87)

VLSItools wanted (0 replies, 10/24/87)

SPICE Implementation (1 reply, 10/27/87)

Magic on HP9000 300 (1 reply, 10/28/87)

IC Layout Software Wanted (0 replies, 10/29/87)

Routing Limitations in Magic? (0 replies, 10/30/87)

Problem with Magic on a SUN 2 (0 replies, 10/30/87)

magic fix for sun3/110 (0 replies, 11/06/87)

SPICE2G6 BUG (0 replies, 11/07/87)

apply for a new member (0 replies, 11/07/87)

Problem with magic on Apollo with DOMAIN/IX 9.5 (1 reply, 11/14/87)

Content Addressable Memory (1 reply, 11/16/87)

IC package acronyms ? (1 reply, 11/19/87)

EDIF parser almost done ... (0 replies, 11/29/87)

Looking for bipolar functional simulator (1 reply, 11/30/87)

Templates for mpanda or panda, anyone ?? (0 replies, 11/30/87)

Desperately Seeking X11 routines for Magic. (0 replies, 11/30/87)

Suprem problems. (0 replies, 12/03/87)

MOSIS TINY FRAME PADS (1 reply, 12/06/87)

Verilog mode for (0 replies, 12/12/87)

EDIF reader/writer wanted (1 reply, 12/14/87)

looking for bdsim (0 replies, 12/18/87)

Text-to-Voice Convertor (0 replies, 12/21/87)

need references on digital logic simulation (0 replies, 12/30/87)

help - magic deallocation problem? (0 replies, 01/05/88)

magic port for MAC II Apple Unix (0 replies, 01/07/88)

VHDL info, -->> EDIF converter (0 replies, 01/08/88)

silicon compiler maillist (0 replies, 01/08/88)

Wanted: DRC script for CMOS on CALMA (0 replies, 01/16/88)

spice2g6 (8 replies, 01/16/88)

request info on PCB generation CAE tools (0 replies, 01/20/88)

Pen plotter software with VLSI Tools?? (2 replies, 01/21/88)

Numerical Computation Newsgroup needed? (9 replies, 01/21/88)

Wanted: 4plane or bw X driver for Magic (1 reply, 01/23/88)

MOSIS Tiny Chip frame and Pad driver... (0 replies, 01/28/88)

X driver (0 replies, 01/29/88)

Magic for Vaxstation II/GPX (2 replies, 01/31/88)

comp.numeric deferred; try Stanford NA list (3 replies, 02/02/88)

New VLSI layout tools from Berkeley ? (1 reply, 02/02/88)

Cells for use with MOSIS tinychip (0 replies, 02/04/88)

mailing list (0 replies, 02/04/88)

Looking for nDOT (2 replies, 02/04/88)

OCT Tools Distribution (0 replies, 02/08/88)

electrostatic plotter software (0 replies, 02/11/88)

IFIP Summer School on VLSI 24 July - 5 August 88, Bergen, Norway (0 replies, 02/11/88)

IFIP VLSI Summer School: Program Abstract (0 replies, 02/12/88)

Looking for a Language? (0 replies, 02/16/88)

Feedback in Crystal (0 replies, 02/17/88)

Berkeley VLSI Tools on HP 300 series Workstations (0 replies, 02/19/88)

Western Digital WD33c93 Controller (0 replies, 02/19/88)

Logic simulation.... (0 replies, 02/24/88)

Wanted LSI simulator (1 reply, 02/24/88)

Magic extraction (4 replies, 02/24/88)

please remove my name (0 replies, 03/01/88)

Porting Mextra (2 replies, 03/04/88)

Help needed with EDIF graphics (1 reply, 03/05/88)

spice under VMS (1 reply, 03/06/88)

Memory size for Berkeley tools (1 reply, 03/07/88)

Berkeley VLSI Tools on Microvax (0 replies, 03/09/88)

EDIF and Schematics (0 replies, 03/10/88)

EDIF, schematics, etc (1 reply, 03/11/88)

EDIF Specifications (4 replies, 03/11/88)

1986 Berkeley tools: Preprocessor problem w/ Meg input file (1 reply, 03/13/88)

Logic simulation survey midMarch results... (0 replies, 03/15/88)

EDIF programmer wanted (0 replies, 03/17/88)

Oct tools (0 replies, 03/18/88)

Posting schematics... (10 replies, 03/19/88)

CIF => PostScript, or Magic => PostScript (0 replies, 03/21/88)

parallel approaches to VLSI routing (0 replies, 03/22/88)

Berkeley Tools: Sim2spice (1 reply, 03/23/88)

CIF => PostScript (0 replies, 03/24/88)

Need bug fix for spice3a7 (0 replies, 03/25/88)

metastability in ASIC synchronizer implementations (6 replies, 03/30/88)

How to unmagic cif files? (1 reply, 03/30/88)

schematic interchange format (6 replies, 04/04/88)

SPICE runs out of machine space? (0 replies, 04/05/88)

Looking for WIRE-WRAP Leadless Chip Carrier (0 replies, 04/06/88)

Available Hardware Testers (3 replies, 04/08/88)

Crystal papers (0 replies, 04/12/88)

Magic bug reports (0 replies, 04/14/88)

re-post of COMPUTALKER Speech Sythesizer for Brad Clements (0 replies, 04/15/88)

EDIF is now an ANSI Standard (1 reply, 04/16/88)

Online parts quotation service (1 reply, 04/16/88)

Eurographics Workshop on Graphics Hardware (1 reply, 04/20/88)

PCB cad systems (0 replies, 04/21/88)

SPICE2 on the RT under 4.3 ? (0 replies, 04/21/88)

Spice3B1 & MOSFETS problems (0 replies, 04/22/88)

EDIF inquiries (0 replies, 04/23/88)

EDIF Tutorial Videotapes (0 replies, 04/23/88)

Question about speech Synthesisor (7 replies, 04/26/88)

HP9000 Berkeley Unix (0 replies, 04/27/88)

Comp. Architecture & Organization (4 replies, 04/29/88)

Magic for the Mac II? (0 replies, 04/30/88)

Logic simulator survey as of April 21, 1988. (4 replies, 05/02/88)

Comp. Architecture survey (1 reply, 05/02/88)

need help with COLLECT function (1 reply, 05/05/88)

Experience with "Electric" (1 reply, 05/06/88)

EDIF to CIF|PostScript|flatEDIF Sources (0 replies, 05/10/88)

MKCP for CMOS (0 replies, 05/16/88)

EDIF2CIF, CIF2EDIF utilities (2 replies, 05/21/88)

Magic for Sun 4 wanted (1 reply, 06/02/88)

Free silicon design software??? (2 replies, 06/11/88)

Ternary Logic Systems (0 replies, 06/14/88)

Silly novice questions on books, courses, etc. (0 replies, 06/17/88)

high capacity memories (0 replies, 06/21/88)

Magic problems (0 replies, 06/21/88)

VLSI design tools (7 replies, 06/23/88)

Bekeley OCT Tools (2 replies, 06/27/88)

more CAD tool notes (0 replies, 06/28/88)

VEM running on X11 ... (0 replies, 06/29/88)

VHDL simulator wanted (0 replies, 07/08/88)

FFT (0 replies, 07/08/88)

EDIF 2 0 0 to GDSII (0 replies, 07/11/88)

Kic and MAGIC for SUN (0 replies, 07/12/88)

Mayo ??? (1 reply, 07/12/88)

EDIF 2 0 0 rom code data and test vectors (1 reply, 07/13/88)

Updating Re: memories (0 replies, 07/13/88)

HSPICE, HILO-3, SILOS (0 replies, 07/13/88)

Chapter 01 - 1076 DoD translated VHDL test suite (0 replies, 07/13/88)

Summary by paragraph of available VHDL tests.. (0 replies, 07/13/88)

Chapter 02 - 1076 DoD translated VHDL test suite (0 replies, 07/13/88)

Chapter 03 - 1076 DoD translated VHDL test suite (0 replies, 07/13/88)

Chapter 05 - 1076 DoD translated VHDL test suite (0 replies, 07/13/88)

Chapter 06 - 1076 DoD translated VHDL test suite (0 replies, 07/13/88)

Chapter 08 - 1076 DoD translated VHDL test suite (0 replies, 07/13/88)

Chapter 09 - 1076 DoD translated VHDL test suite (0 replies, 07/13/88)

Chapter 13 - 1076 DoD translated VHDL test suite (0 replies, 07/13/88)

Chapter 14 - 1076 DoD translated VHDL test suite (0 replies, 07/13/88)

VHDL-mode for gnu-emacs editor (0 replies, 07/13/88)

GNUEMACS kbd macro aids for translating 7.2 VHDL to 1076 VHDL (0 replies, 07/13/88)

Chapter 07 - 1076 DoD translated VHDL test suite (1 reply, 07/14/88)

Chapter 04 - 1076 translated DoD VHDL test suite (0 replies, 07/14/88)

Coversion from caesar to magic form (0 replies, 07/15/88)

memories (5 replies, 07/16/88)

Magic driver for X-11 available from expo (0 replies, 07/20/88)

multimegabit memories (0 replies, 07/21/88)

MOSIS announcement (0 replies, 07/22/88)

Wanted: 4Plane CMap and DStyle files for Magic (0 replies, 07/22/88)

Current version of Spice? (1 reply, 07/22/88)

Recent postings about VHDL..did they get distributed OK? (0 replies, 07/22/88)

EDIF User Group Dial up BBS (0 replies, 07/27/88)

need VT2XX terminal with Tek emulation for spice (0 replies, 07/28/88)

Circuits that break simulators wanted (0 replies, 07/30/88)

Where to start in lsi (0 replies, 08/09/88)

Problems noted in Recent VHDL shared test suite.. (0 replies, 08/23/88)

Single Error Detection (0 replies, 08/25/88)

GaAs integrated circuits (0 replies, 09/01/88)

VPNR: A software package for standard cell place and route (0 replies, 09/02/88)

More X11 magic drivers (0 replies, 09/03/88)

Dense VLSI Packaging (0 replies, 09/04/88)

CMOS3 cells in Oct (0 replies, 09/07/88)

EDIF user group (0 replies, 09/20/88)

IEEE NEWS GROUP (3 replies, 09/20/88)

Help with magic on Apollo 4000 (0 replies, 09/21/88)

Decennial Caltech Conference on VLSI -- Announcement & Call for Papers (0 replies, 09/24/88)

Delight.Spice for HP 9000's ? (0 replies, 09/29/88)

Edif Example Files-- Part 1 of 23 (0 replies, 10/07/88)

Edif Example Files-- Part 2 of 23 (0 replies, 10/07/88)

Edif Example Files-- Part 3 of 23 (0 replies, 10/07/88)

Edif Example Files-- Part 4 of 23 (0 replies, 10/07/88)

Edif Example Files-- Part 5 of 23 (0 replies, 10/07/88)

Edif Example Files-- Part 6 of 23 (0 replies, 10/07/88)

Edif Example Files-- Part 7 of 23 (0 replies, 10/07/88)

Edif Example Files-- Part 8 of 23 (0 replies, 10/07/88)

Edif Example Files-- Part 9 of 23 (0 replies, 10/07/88)

Edif Example Files-- Part 10 of 23 (0 replies, 10/07/88)

Edif Example Files-- Part 11 of 23 (0 replies, 10/07/88)

comp.lsi ... this is totally out of control (0 replies, 10/09/88)

Edif Example Files-- Part 13 of 23 (0 replies, 10/10/88)

Edif Example Files-- Part 14 of 23 (0 replies, 10/10/88)

Edif Example Files-- Part 15 of 23 (0 replies, 10/10/88)

Edif Example Files-- Part 16 of 23 (0 replies, 10/10/88)

Edif Example Files-- Part 17 of 23 (0 replies, 10/10/88)

Edif Example Files-- Part 18 of 23 (0 replies, 10/10/88)

Edif Example Files-- Part 19 of 23 (0 replies, 10/10/88)

Edif Example Files-- Part 12 of 23 (3 replies, 10/10/88)

What is EDIF anyway? (0 replies, 10/11/88)

EDIF Tokenizer (0 replies, 10/11/88)

Apology, further Explanation on EDIF EXAMPLES (2 replies, 10/12/88)

Edif Files-- Part n of 00 (0 replies, 10/12/88)

definition, please (1 reply, 10/12/88)

VLSI Testing, Questionnaire (0 replies, 10/13/88)

looking for codec information (0 replies, 10/18/88)

Summary - Parallel implementations of VLSI CAD Tools (0 replies, 10/21/88)

Edif Example Files-- Part 20 of 23 (0 replies, 10/29/88)

Edif Example Files-- Part 21 of 23 (0 replies, 10/29/88)

Edif Example Files-- Part 22 of 23 (0 replies, 10/29/88)

Edif Example Files-- Part 23 of 23 (0 replies, 10/29/88)

Magic/VIVID/whatever Users: AED 512 for sale (0 replies, 11/09/88)

CIF to GDS2 Conversion (3 replies, 11/11/88)

KIC to HPGL wanted (1 reply, 11/11/88)

SCMOS.TECH for Magic (1 reply, 11/12/88)

Analog pads (0 replies, 11/12/88)

Meg -> endot (0 replies, 11/17/88)

mpla tiles (2 replies, 11/17/88)

meg fix (0 replies, 11/17/88)

DON'T UPDATE YOUR MEG's (0 replies, 11/17/88)

EDIF -- ftp access to recent samples? (0 replies, 11/20/88)

SLIC Improved (0 replies, 11/24/88)

SLIC Update (0 replies, 11/24/88)

SLIC Updated Source Code (0 replies, 11/24/88)

SUN interface for Spice3 (1 reply, 11/24/88)

enhancement to magic/ext2sim/sim2spice (0 replies, 11/30/88)

public domain schematic editor (0 replies, 12/03/88)

What happened to comp.lsi.cad? (1 reply, 12/09/88)

Surface mounted packages (1 reply, 12/15/88)

Hughes' 3-D Processor Array (3 replies, 12/15/88)

Getting started in LSI/system design (0 replies, 12/20/88)

Display techniques/ HELP! (0 replies, 01/07/89)

Software Sought (0 replies, 01/07/89)

Grid Array Socket (0 replies, 01/12/89)

SPICE3a7 operation... (0 replies, 01/13/89)

Magic modifications wanted (0 replies, 01/13/89)

Help: Would you share your experience on schematic capture tools? (0 replies, 01/26/89)

Public Domain simulator wanted. (0 replies, 01/26/89)

cif filters? (2 replies, 02/01/89)

CAD Framework Initiative Meeting on FEB 16-17 and CFI info (0 replies, 02/02/89)

Network Definition Language (1 reply, 02/02/89)

Help hooking Versatec plotter to Suns (0 replies, 02/04/89)

In Circuit Emulator for PS/2 (0 replies, 02/04/89)

Circuit problem (1 reply, 02/09/89)

Semiconductor technology with fault tolerance features built-in (0 replies, 02/11/89)

Mentor Graphics software (2 replies, 02/18/89)

Synthesis and Testing (0 replies, 02/19/89)

CIF -> HPGL (1 reply, 02/19/89)

CMOS Process Parameters for Spice (0 replies, 02/21/89)

MAGIC on MicroVAX (1 reply, 02/21/89)

Magic on 386 Machines? (0 replies, 02/22/89)

The 3 inverter problem (6 replies, 02/22/89)

Macro Cells in scmos technology (0 replies, 02/22/89)

USER MANUAL for SPICE3A7 (0 replies, 02/23/89)

Problem reading GDS into Magic (2 replies, 02/24/89)

"CIFP" Package for HP 7570A Plotter (0 replies, 02/24/89)

"4 phase clocks" (0 replies, 02/25/89)

Full solution, inverter problem (0 replies, 02/25/89)

noninverting, Threshold Logic (0 replies, 02/26/89)

Call for discussion - PROPOSED EDIF news group (0 replies, 02/27/89)

9th Conference On Foundations of Software Technology and Theoretical Computer Science, INDIA (0 replies, 03/15/89)

Call for discussion - Proposed VHDL News Group (2 replies, 03/28/89)

Magic tech file for floating gates ... (0 replies, 03/31/89)

CIF from 'The VLSI Designer's Library' (0 replies, 04/02/89)

predicted yield of BIG microprocessors (3 replies, 04/02/89)

Wired-OR in VLSI (4 replies, 04/05/89)

Sim2scope and caesar in Sun 3/60 (0 replies, 04/05/89)

Spice2g6 Memory Limit Problem (0 replies, 04/06/89)

desperately seeking polygon help (0 replies, 04/06/89)

Looking for Calma GDS II specification ! (0 replies, 04/07/89)

SLIC Version 1.2 (0 replies, 04/09/89)

Faster than SPICE (2 replies, 04/12/89)

CAzM circuit simulator (1 reply, 04/14/89)

Parallel Simulated Annealing / References and Are You Doing It? (0 replies, 04/14/89)

Hot Chips Symposium (1 reply, 04/15/89)

Announcement (0 replies, 04/16/89)

VHDL description wanted (4 replies, 04/18/89)

ICCAD (1 reply, 04/18/89)

Latest Vivid features? (2 replies, 04/22/89)

pcb newsgroup (0 replies, 04/22/89)

Configuration Management - A question (0 replies, 04/27/89)

micro probe for analog integrated circuits (0 replies, 04/28/89)

KIC2 question (0 replies, 04/30/89)

Looking for e-mail addresses (0 replies, 05/02/89)

3rd European EDIF Forum (0 replies, 05/03/89)

is there nobody using catia (0 replies, 05/09/89)

Thanks for replies to request (0 replies, 05/09/89)

Ella example designs wanted (0 replies, 05/09/89)

Need a file from BOLD distribution ... (0 replies, 05/10/89)

LSI CAD tool opinions wanted (4 replies, 05/10/89)

IC Probes (0 replies, 05/11/89)

Cad system needed (0 replies, 05/18/89)

Is anyone out there using Xilinx chips? (0 replies, 05/20/89)

Summer Position; CAD Tools Development (0 replies, 05/22/89)

Spice problem on Ultrix-32 V3.0 (0 replies, 05/26/89)

IEEE Standards activities --> Info on Design Automation Stds (0 replies, 05/27/89)

Oct Tool Set Question.......... (1 reply, 05/30/89)

A MODIFIED Call for discussion - Proposed VHDL News Group (2 replies, 06/01/89)

EDIF (6 replies, 06/01/89)

CMOS3 and CMOS2 cell libraries; CMOS VLSI Design Book (1 reply, 06/06/89)

VHDL Simulator (2 replies, 06/10/89)

Spice 3c1. (0 replies, 06/13/89)

Mixed mode simulation for chip design (6 replies, 06/14/89)

Spice 3 (5 replies, 06/14/89)

Berkeley SIM datafile format needed. (0 replies, 06/20/89)

Transistor sizing (1 reply, 06/20/89)

Glueing analog/digital simulators for mixed mode simulation (1 reply, 06/21/89)

Need help: Problems with ULTRIX 3.0, SPICE 2,3 (0 replies, 06/29/89)

Latest version of MAGIC (2 replies, 06/29/89)

Need: Spice source file unix.c for Sun 3 system. (1 reply, 06/30/89)

Large simulations wanted (0 replies, 07/02/89)

Would like ESPRESSO option: -do single_output (0 replies, 07/05/89)

Public Domain IDL Compilers (0 replies, 07/06/89)

Unix VLSI CAD Systems an Tools (0 replies, 07/06/89)

Unix VLSI CAD Systems and Tools (0 replies, 07/06/89)

ASIC FAE and ASIC Designer Positions Available (0 replies, 07/12/89)

Large Variety of Computer and Electronics Equipment possible reposting (1 reply, 07/15/89)

Extended Precision 2's Complement Multiply? (0 replies, 07/27/89)

GaAs CMOS in Cray-3 ? (4 replies, 07/28/89)

Wanted: Daisy's MAX manual.... (0 replies, 08/01/89)

VEM and/or Rick Spickelmier (0 replies, 08/03/89)

Third European EDIF Forum (0 replies, 08/03/89)

Spice Level 3 charge modeling (0 replies, 08/04/89)

IC LAYOUT DESIGN INFO (1 reply, 08/08/89)

spice (0 replies, 08/11/89)

Junior/Senior Positions in CAE/Logic Simulation Available in Silicon Valley (0 replies, 08/13/89)

EDIF NETLIST examples (0 replies, 08/15/89)

SCS Simulation Manager info request (0 replies, 08/18/89)

Job Openings at Intel-Folsom, Ca (0 replies, 08/24/89)

Modem chip set from Sierra OK ?? (0 replies, 08/25/89)

EDIF World is Near (0 replies, 08/30/89)

new MOSIS' SCMOS.TECH for Magic4.10 ..... (0 replies, 08/30/89)

Synchronizer failure; MTBF (1 reply, 09/05/89)

Looking for KIC2 sources running under X11 (0 replies, 09/13/89)

Arbiter / Synchronizer failure; MTBF (0 replies, 09/15/89)

Analog vlsi simulation: Summary (0 replies, 09/16/89)

BSIM model in SPICE (0 replies, 09/16/89)

EDIF Draft Standard Available? (1 reply, 09/17/89)

MPLA patch request (0 replies, 09/17/89)

FABRICS II user guide (0 replies, 09/17/89)

Magic Version 6 BETA test sites wanted (0 replies, 09/19/89)

Benchmark Digital Circuits for testing Simulator (0 replies, 09/21/89)

How to get Boyer-Moore Theorem Prover (0 replies, 09/27/89)

Magic and color postscript... (0 replies, 09/28/89)

octtools or Menter Graphics' package (2 replies, 10/01/89)

Electric & Magic (0 replies, 10/03/89)

3rd European EDIF Forum -- Preliminary Programme 12,13 October 1989 (0 replies, 10/03/89)

4 bit full adder w/CLA for MOSIS 2 micron pwell scmos process (0 replies, 10/04/89)

SCMOS Op-Amp Cell (1 reply, 10/05/89)

RSIM questions and availability (0 replies, 10/06/89)

cdrc info desired (0 replies, 10/11/89)

Associative/Content Addressable memories & processors (0 replies, 10/12/89)

Usenet / Internet test (0 replies, 10/13/89)

CAM circuit information request (0 replies, 10/17/89)

Cadence anyone? (0 replies, 10/18/89)

Software Needed Urgently! (0 replies, 10/19/89)

On-Line Detection (2 replies, 10/19/89)

WOM reference needed (1 reply, 10/20/89)

ground bounce (1 reply, 10/20/89)

References needed for layout cap algorithm and comm. ambiguity (0 replies, 10/23/89)

Transient faults in memories (2 replies, 10/24/89)

Survey Results (0 replies, 10/25/89)

Cadence mailing list found (0 replies, 10/25/89)

VHDL test examples (4 replies, 10/25/89)

RSIM simulator (1 reply, 10/25/89)

SPICE for CRAY-2 (0 replies, 11/10/89)

request info - magic on 3100? (0 replies, 11/13/89)

RS-232 5V (3 replies, 11/14/89)

ISCAS netlists (2 replies, 11/15/89)

PD EDIF v200 syntax checker for IBM PC (0 replies, 11/16/89)

ISCAS '85 test vectors? (0 replies, 11/17/89)

cif/magic printing (0 replies, 11/17/89)

Path Programmable Logic (0 replies, 11/19/89)

Microelectronics/VLSI Design Opening at U.Patras (0 replies, 11/19/89)

Floorplanning Package (0 replies, 11/20/89)

Skill (0 replies, 11/20/89)

plotting (0 replies, 11/21/89)

plots (0 replies, 11/21/89)

Need help on Silos input commands ... (3 replies, 11/22/89)

+ 5 volt RS-232 devices (0 replies, 11/22/89)

Trans. on VLSI 11/21/89 (0 replies, 11/22/89)

Talk us out of using SPICE (0 replies, 11/27/89)

Circuit Simulator Benchmarks (6 replies, 11/29/89)

Teletext Receivers (0 replies, 11/29/89)

Teletext Chips (0 replies, 11/30/89)

Plotting Magic/Cif (0 replies, 12/01/89)

Summer School on Formal Methods for VLSI Design (0 replies, 12/04/89)

test (0 replies, 12/05/89)

Modeling SnapBack characteristics for Circuit Simulation (0 replies, 12/05/89)

Research Assistant job (0 replies, 12/05/89)

IEEE Computer Society 1990 VLSI Workshop (0 replies, 12/08/89)

LSI equipment for sale (0 replies, 12/13/89)

Amd/Xilinx LCA's (0 replies, 12/13/89)

Spice written in the C language: Is there one, ftp site? (0 replies, 12/13/89)

ISSCC errata (1 reply, 12/14/89)

Single_output option of ESPRESSO (0 replies, 12/19/89)

Looking for newer versions of Crystal (0 replies, 12/19/89)

test sites needed ... (1 reply, 12/20/89)

Gate Array Design Program for IBM PC-AT (0 replies, 01/04/90)

Computer Engineering/Computer Science Monograph (0 replies, 01/05/90)

Artificial Intelligence Editor Wanted (0 replies, 01/05/90)

Journal/Progress Series authors wanted (0 replies, 01/05/90)

Large CIF files needed (0 replies, 01/05/90)

Source for Timberwolf4.2 (0 replies, 01/07/90)

MOSIS' net-list-to-parts test sites... (0 replies, 01/11/90)

Moore's Law (0 replies, 01/13/90)

Fault Simulation (0 replies, 01/13/90)

1990 IEEE-CS Workshop on VLSI (0 replies, 01/13/90)

1990 VLSI Workshop (0 replies, 01/13/90)

Research assistant (0 replies, 01/13/90)

looking for ideas (1 reply, 01/18/90)

Wanted? An overview of Octtools (0 replies, 01/18/90)

magic (1 reply, 02/08/90)

Mpla Templates (0 replies, 02/08/90)

CORDIC algorithm for trig (0 replies, 02/09/90)

looking for e-beam resist (0 replies, 02/09/90)

HELP - MOS (0 replies, 02/13/90)

PD EDIF parser. (0 replies, 02/13/90)

BiCMOS (0 replies, 02/13/90)

Japanese fuzzy-logic computers (0 replies, 02/14/90)

Call for Papers, Advanced Research in VLSI Conference, March 1991 (0 replies, 02/23/90)

Microelectronic System Education Call for Papers (0 replies, 02/23/90)

Two positions (0 replies, 02/24/90)

Help: is there anyone willing to let me ftp "wombat" from UCB? (0 replies, 02/28/90)

Floating Point Multipliers (0 replies, 03/04/90)

Again, about my RC network question. (0 replies, 03/05/90)

A Question On Biasing Circuits (4 replies, 03/05/90)

spice2G6 for DEC3100 (0 replies, 03/06/90)

OCTTOOLS MISII Synthesis Questions (1 reply, 03/19/90)

Fault grading of VLSI (0 replies, 03/21/90)

call for discussion "boundary scan" (1 reply, 03/22/90)

VHDL, JEDEC, CUPL info wanted (0 replies, 04/10/90)

Wanted: references on routing algorithms. (3 replies, 04/11/90)

Verilog Swap Space (0 replies, 04/11/90)

In Search of Hardware Description Program (0 replies, 04/12/90)

Routing of power/ground nets. (0 replies, 04/14/90)

low-cost VLSI testers (0 replies, 04/14/90)

CFP - EDIF WORLD `90 (0 replies, 04/26/90)

Info on Public Domain VHDL Package (0 replies, 05/06/90)

circuit simulatots (0 replies, 05/26/90)

Summary -- arithmetic operators using octtools (0 replies, 05/29/90)

gerber format (0 replies, 05/30/90)

Research Fellow / Research Associate (0 replies, 05/30/90)

High Level Synthesis (1 reply, 05/31/90)

Results of X windows CAE/EDA survey. (0 replies, 05/31/90)

BDNET -> SPICE. Anyone know how? (0 replies, 06/01/90)

VLSI TOOLS (0 replies, 06/02/90)

standard cell based synthesis (0 replies, 06/04/90)

SEEK REFERENCE FOR INCOMPLETE OR PARTIAL VALUED LOGIC IN VLSI CIRCUITS (0 replies, 06/05/90)

reverse engineering (2 replies, 06/06/90)

Alliant PAX information (0 replies, 06/06/90)

A Truly Secure (7 replies, 06/08/90)

CIF specifications request (1 reply, 06/09/90)

notes on 64Mbit DRAM paper from Hitachi (0 replies, 06/13/90)

Question about netlist description in EDIF 200 (1 reply, 06/15/90)

Call for Papers, Adv. Research in VLSI 1991 (0 replies, 06/29/90)

CLSI VHDL Tool Integration Platform (0 replies, 07/05/90)

Need gate level logic simulator (0 replies, 07/10/90)

Technology Transfer Mailing List (0 replies, 07/12/90)

Seeking a lisp.h file for Chris Terman's RSIM, etc. (0 replies, 07/14/90)

VLSI for AI and Neural Nets Workshop. Oxford, England Sept.'90 (0 replies, 07/14/90)

VLSI/MicroChip Design Tools (5 replies, 07/18/90)

VLSI Education Conference (0 replies, 07/21/90)

The `Common Simulation Data Format (0 replies, 07/23/90)

"L" language (0 replies, 07/24/90)

Annoucement European EDIF Forum 1990 (0 replies, 07/25/90)

Anybody compiled SPICE2G.6 on a Cray? (0 replies, 07/26/90)

2um nwell pads (0 replies, 07/27/90)

Commercial sources for associative memories? (1 reply, 07/28/90)

EDIF World `90 (0 replies, 07/29/90)

[Wanted] Maclogic & MacBridge (0 replies, 07/30/90)

VLSI Design Tools on PCs (6 replies, 07/30/90)

Microelectronic Conference - Invitation and Program (0 replies, 08/02/90)

Electro-optic bus (15 replies, 08/03/90)

Verilog HDL vs VHDL (0 replies, 08/04/90)

HDLs (0 replies, 08/05/90)

Looking for DRAM design (1 reply, 08/09/90)

Book on Verilog HDL (4 replies, 08/10/90)

Papers due Sept. 15 for JSSC (0 replies, 08/11/90)

PALASM (0 replies, 08/12/90)

no PALASM90 on workstations (18 replies, 08/12/90)

pld design environments (0 replies, 08/13/90)

ESDI and IPI controllers (0 replies, 08/14/90)

VHDL Standard Logic Package (0 replies, 08/14/90)

CAD tools for Silicon Micromachining (0 replies, 08/14/90)

Viewlogic Workview 860 suite (0 replies, 08/20/90)

Any MAGIC wizards out there ? (0 replies, 08/20/90)

Optical bus (0 replies, 08/22/90)

VLSI for AI and Neural Nets Workshop. Oxford, Sept. 5-7 (0 replies, 08/22/90)

velocity sensing for robotic joints (10 replies, 08/22/90)

MAGIC to postcript (0 replies, 08/24/90)

X-servers (0 replies, 08/30/90)

Magic on DOS (0 replies, 08/31/90)

help with large SPICE simulations (5 replies, 09/01/90)

CALMA systems for sale (0 replies, 09/11/90)

Need a channel router (0 replies, 09/12/90)

SASIMI'90 (0 replies, 09/12/90)

VHDL mailing list (0 replies, 09/12/90)

Some info on VHDL (1 reply, 09/13/90)

Orbit/Foresight 1.2um twin well Magic design rules file (0 replies, 09/14/90)

D-algorithm implementation (0 replies, 09/14/90)

Full-Custom VLSI Design -- Employment Wanted. (0 replies, 09/17/90)

Looking for info on video chips (0 replies, 09/19/90)

Wanted: CMOS differential driver/receiver I/O cell (0 replies, 09/21/90)

Looking for DELIGHT (0 replies, 09/25/90)

Fugu: 3D tool for Pisces IIB & Suprem IV (0 replies, 09/26/90)

Fugu: PostScript example (0 replies, 09/26/90)

Info wanted on MBR for digital hardware diagnosis (0 replies, 09/27/90)

edge triggered or self-clocked logic (2 replies, 09/27/90)

ASICs and other IC questions (0 replies, 09/28/90)

Magic Version 6 now available (1 reply, 09/28/90)

Berkeley VLSI Tools besides Magic? (0 replies, 09/30/90)

Question: EDIF version? (0 replies, 10/01/90)

A mailing list to discuss the Verilog HDL. (0 replies, 10/01/90)

crystal (0 replies, 10/03/90)

Need help addressing Futurenet mouse card (0 replies, 10/04/90)

VLSI Designers Wanted (0 replies, 10/04/90)

Channels Wanted (0 replies, 10/06/90)

Asynchronous system / "self-clocked" design - a survey TR available (0 replies, 10/08/90)

who is your favorite ASIC/Custom IC vendor? (3 replies, 10/09/90)

..more on the asynchronous Technical Report.. (0 replies, 10/09/90)

Periodicals, Journals and Books on design (0 replies, 10/10/90)

CALL FOR DISCUSSION comp.lang.vhdl (0 replies, 10/15/90)

BiCMOS through MOSIS (1 reply, 10/17/90)

Wanted: Electronic CTE Failure Data (1 reply, 10/18/90)

Graph-based IR (0 replies, 10/18/90)

1991 Advanced Research in VLSI paper deadline extended (0 replies, 10/19/90)

Information about new book on parallel processing and VLSI (0 replies, 10/22/90)

Looking for SPICE doc's (0 replies, 10/24/90)

Evaluation of Cadence VLSI Tools Wanted (0 replies, 10/25/90)

Simulation Workshop (0 replies, 10/25/90)

Magic V6 on magnetic tape (0 replies, 10/26/90)

VHDL (2 replies, 10/27/90)

CMOS 2um SPICE parameters (0 replies, 10/27/90)

Analog magic cells (0 replies, 10/31/90)

plotting from magic 6 (0 replies, 11/01/90)

Valid S320 and/or ScaldStar forsale (0 replies, 11/02/90)

Unix to HP16500A logic analyzer? (0 replies, 11/04/90)

Summary: Graph-based intermediate representations. (0 replies, 11/04/90)

Pisces IIb... (0 replies, 11/05/90)

VHDL model of a DMA controller (0 replies, 11/06/90)

EDIF info needed (0 replies, 11/07/90)

IRSIM parameter file for 1.2um MOSIS SCMOS (0 replies, 11/07/90)

Used Actel part (0 replies, 11/08/90)

references needed (0 replies, 11/08/90)

Need to use the Magic database for layer representation (0 replies, 11/09/90)

SCS/Mentor users group? (1 reply, 11/10/90)

RS6000 and CAD Tools (1 reply, 11/11/90)

Error in net-address. (0 replies, 11/11/90)

paper needed (0 replies, 11/14/90)

Query on the accuracy of circuit simulators (0 replies, 11/14/90)

PCB Router (0 replies, 11/16/90)

What is the newest version of Crystal? (0 replies, 11/16/90)

XYMASK to CIF conversion (0 replies, 11/17/90)

Need help with PALASM2 (0 replies, 11/17/90)

npn tranistors in magic (1 reply, 11/20/90)

SPICE3 for X11R4? (1 reply, 11/21/90)

Faculty Positions (0 replies, 11/21/90)

VHDL-model for an 8-bit processor (0 replies, 11/22/90)

CALL FOR VOTES: comp.lang.vhdl (1 reply, 11/26/90)

MAGIC VLSI FONTS (0 replies, 11/27/90)

Course on Formal Methods (0 replies, 11/28/90)

cif2ps (1 reply, 11/29/90)

SPICE3, spice@cad.berkeley.edu (2 replies, 11/29/90)

Physical Design Workshop II (0 replies, 12/02/90)

ACNN'91 Tutorials Program (0 replies, 12/06/90)

MCNC Sequential Test benchmarks (0 replies, 12/06/90)

NPN device characteristics in SCNA20? (1 reply, 12/07/90)

Converting from .cif to post script (0 replies, 12/11/90)

Research Assistantships in Formal Methods in VLSI (0 replies, 12/12/90)

Scaling from 3.0um technology to 1.25um technology (0 replies, 12/13/90)

Survey of HDL users (0 replies, 12/13/90)

info regarding vhdl (3 replies, 12/13/90)

University of Pittsburgh VHDL Simulator (0 replies, 12/14/90)

Need magic files of channel routings (0 replies, 12/14/90)

ACE Hardware Description Language (0 replies, 12/14/90)

Verilog educational use (1 reply, 12/15/90)

Verilog test vectors into LSI .TPT and .SCL files anyone ? (0 replies, 12/18/90)

MAGIC ver 6.3 ---Is FET resistance set to zero? (1 reply, 12/19/90)

VTIP (0 replies, 12/20/90)

comp.lang.vhdl passes successfully (0 replies, 12/21/90)

Need info for LSI CAD's for a PC (2 replies, 12/26/90)

Yield data wanted - 1 micron CMOS (1 reply, 01/04/91)

VHDL Pretty-printer (1 reply, 01/05/91)

Senior Design Engineer (0 replies, 01/05/91)

newsgroup for VHDL (0 replies, 01/07/91)

SIS logic optimizer (0 replies, 01/08/91)

1991 IEEE-CS VLSI Worskhop (0 replies, 01/08/91)

CHDL'91 (1 reply, 01/08/91)

Newest versions of Magic 6 and Spice 3 (1 reply, 01/15/91)

Magic 1.25um Scmos Pad Frames & Pads (1 reply, 01/17/91)

need translator to generate magic file from yacr output (0 replies, 01/18/91)

startup problems with Magic 6.3 (1 reply, 01/23/91)

advanced research in VLSI conference 25--27 March (0 replies, 01/23/91)

CFP DCC-92 (0 replies, 01/24/91)

1991 IEEE-CS VLSI Workshop (0 replies, 01/24/91)

Multi-port RAMs (4 replies, 01/25/91)

membership (1 reply, 01/29/91)

Benchmarks for Boundary Scan (0 replies, 01/30/91)

What VHDL simulators handle WAVES at this point? (0 replies, 01/30/91)

want logic simulation program (0 replies, 01/31/91)

high voltage power-device simulator (0 replies, 01/31/91)

VLSI in Siberia (0 replies, 01/31/91)

VLSI Software (2 replies, 02/01/91)

Porting Magic6.0 onto the RS6000 (0 replies, 02/04/91)

VHDL public domain software (2 replies, 02/04/91)

Need info about CFI (0 replies, 02/04/91)

Need info on CFI (0 replies, 02/05/91)

Need DRAM generator (0 replies, 02/06/91)

Call for Contributions: Oxford Field Programmable Logic Workshop (0 replies, 02/06/91)

The LSI Cottage Industry (0 replies, 02/06/91)

Question: Analog delay element (0 replies, 02/07/91)

About logic simulator (1 reply, 02/07/91)

JTAG specs (0 replies, 02/07/91)

vhdl puzzle (3 replies, 02/08/91)

CIF->PS VLSI geometry description (1 reply, 02/08/91)

New Journal/Call for Papers (0 replies, 02/09/91)

Effective Resistance of MOSFETs (1 reply, 02/11/91)

SPICE parameters for GaAs BJT's or diodes (3 replies, 02/11/91)

DAZIX software on X terminals ? (0 replies, 02/12/91)

Magic 6.x on SparcStation bug? (1 reply, 02/14/91)

MOSIS info wanted (0 replies, 02/14/91)

MOSIS costs (0 replies, 02/15/91)

VLSI 91 Call (0 replies, 02/15/91)

Placement-benchmarks (0 replies, 02/15/91)

need help: MOSIS' CMOS parasitic bipolar transistor charateristic (0 replies, 02/16/91)

Muller C-Elements (0 replies, 02/17/91)

Volume chip costs. (2 replies, 02/17/91)

<<>> HELP! - AES/EBU formating <<>> (0 replies, 02/18/91)

BSDL parser (0 replies, 02/20/91)

Magic for DOS (0 replies, 02/21/91)

CALL FOR PARTICIPATION: Hot Chips Symposium III (1 reply, 02/22/91)

SPICE parameters for low-voltage process (0 replies, 02/22/91)

References on Object Oriented VLSI CAD, please? (0 replies, 02/26/91)

DFT91 - CALL FOR PAPERS (0 replies, 02/26/91)

Cost of VLSI production? (0 replies, 02/27/91)

Verilog mode for GNU emacs (0 replies, 03/02/91)

Mpla and magic 6.3 (0 replies, 03/02/91)

estimating layout area of IC function blocks (0 replies, 03/04/91)

Info-VLSI dead (0 replies, 03/04/91)

Call for Papers - WSI Architectures (0 replies, 03/04/91)

Lengths data from CIF files (0 replies, 03/06/91)

Full complementary CMOS tiles for mpla? (0 replies, 03/06/91)

IRSIM and Magic 6.3, tut11a (0 replies, 03/09/91)

Olympus Synthesis (0 replies, 03/09/91)

Public Access Software (0 replies, 03/10/91)

Friendly Interface to MOSSIM available? (0 replies, 03/13/91)

INTO CLASS PROJECTS (0 replies, 03/13/91)

User Friendly MOSSIM Avaliable? (0 replies, 03/13/91)

Explaination of SPICE3C1 Messages Needed (1 reply, 03/14/91)

VLSI Conference, March 25-27 (0 replies, 03/14/91)

Magic Tutorial: Ckt. Extraction (1 reply, 03/14/91)

Need help: layout of floating-gate MOS transistor (0 replies, 03/15/91)

VLSI-chemical level design (0 replies, 03/15/91)

magic well contact problem (0 replies, 03/19/91)

Berkely Spice (0 replies, 03/19/91)

Looking for information (0 replies, 03/20/91)

SPICE parameters for a typical DRAM process? (0 replies, 03/20/91)

How to plot *.cif (0 replies, 03/21/91)

OCT 4.0 on SPARCstation (1 reply, 03/22/91)

To find new Magic Package (0 replies, 03/22/91)

RFD: comp.lsi.cat (0 replies, 03/22/91)

clock multiplication (0 replies, 03/22/91)

How can I ... (0 replies, 03/24/91)

Formation of comp.lsi.cad.test (0 replies, 03/28/91)

Regional Conference on Microelectronics & Systems (0 replies, 03/28/91)

Help (1 reply, 03/28/91)

Formation of the newsgroup Comp.lsi.cat (0 replies, 03/28/91)

comp.lsi.cat (0 replies, 03/28/91)

Computer Aided Test Group (0 replies, 03/30/91)

VLSI CAD & IC Design Automation (0 replies, 03/30/91)

Minimizing Logic (0 replies, 04/01/91)

CFP: IEEE Trans. on Computer - Fault-Tolerant Computing (0 replies, 04/03/91)

I'm seeking part time job (0 replies, 04/04/91)

DAC 91 (0 replies, 04/05/91)

VLSI tester recommendation sought (0 replies, 04/05/91)

Information about Regional Conference (0 replies, 04/05/91)

edge2.1 symbolic layout and ES2 technology?? (0 replies, 04/08/91)

Call For Discussion: Comp.lsi.CAT (9 replies, 04/09/91)

EDIF data (1 reply, 04/11/91)

Graduate program with Assistantship info needed (0 replies, 04/11/91)

RFD: comp.lsi.testing (0 replies, 04/11/91)

Info on FIFOs (0 replies, 04/11/91)

10th Symposium on Computer Arithmetic (0 replies, 04/12/91)

Viewer for Spice, ESIM, RNL, HILO, and CAZM (0 replies, 04/15/91)

Caltech VLSI CAD Tool Distribution (0 replies, 04/18/91)

WANTED !! hard to test logic circuit (0 replies, 04/18/91)

MPLA tech. files for the latest MOSIS design rules (0 replies, 04/19/91)

router effeciency (0 replies, 04/21/91)

Info Needed on More, Difficult Examples for Global Router (0 replies, 04/21/91)

neural network reprints available (0 replies, 04/24/91)

Information about test equipment (1 reply, 04/24/91)

EDIF Parser (3 replies, 04/24/91)

Conference on VLSI Design (0 replies, 04/24/91)

NSF Faculty Workshop on Electronic Design Automation (0 replies, 04/24/91)

Sigview Documentation Update (0 replies, 04/24/91)

call for papers (1 reply, 04/25/91)

Wanted: MAGIC Source Code (0 replies, 04/26/91)

MOSIS Email Address (0 replies, 04/29/91)

Want cell level (1 reply, 04/30/91)

SEDAL Seminar Series (0 replies, 04/30/91)

Questions for chipmunk (0 replies, 04/30/91)

comp.arch (1 reply, 04/30/91)

1st CFV: comp.lsi.testing (1 reply, 04/30/91)

CFP: Defect and Fault Tolerance (0 replies, 04/30/91)

CFP: Defect and Fault Tolerance Workshop (0 replies, 04/30/91)

ACTEL vs XILINX FPGA info needed (0 replies, 05/01/91)

CFV: comp.lsi.testing (0 replies, 05/01/91)

Magic ported on IBM-PC? (1 reply, 05/03/91)

THE THIRD PHYSICAL DESIGN WORKSHOP (0 replies, 05/05/91)

The ISCAS-85 bencmark circuits...Is layout available?? (0 replies, 05/05/91)

VLSI 91 Conference (1 reply, 05/07/91)

Free CAD Utility Tools (0 replies, 05/07/91)

Xwindows based kic (0 replies, 05/09/91)

Symbolic simulation/abstract execution of proderal languages (0 replies, 05/11/91)