frazier@oahu.cs.ucla.edu (11/17/88)
Hello, People.
I am in the process of debugging my design.
A central component of my layout is a finite state
machine. I have designed the fsm with meg (distributed
with Berkeley VLSI tools), and intend to use
espresso and/or nova to reduce it and mpla to
lay it out. However, what I want to do now is to
test the design with endot. Meg provides the -n flag
to generate endot code. Unfortunately, it produces
erroneous code. For endot to work, several pairs of
parens need to be introduced, and some concated bit
strings need to be zero extended. Has anybody implemented
this fix already?
Greg
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Greg Frazier o Internet: frazier@CS.UCLA.EDU
CS dept., UCLA /\ UUCP: ...!{ucbvax,rutgers}!ucla-cs!frazier
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