[comp.lsi] Chapter 01 - 1076 DoD translated VHDL test suite

grout@cadillac.stars.flab.Fujitsu.JUNET (Steve Grout) (07/13/88)

This is Chapter 01 of a 1076-1987 VHDL test suite which was translated
from an 7.2 VHDL version test suite
developed by Intermetrics under funding by the DoD.  These tests
have been verified todate mainly against a VHDL 'recognizer' so they
may yet have problems with VHDL semantics.  They consist of two
classes of tests, 

  ERROR Tests: - names which start with 'e' should result in VHDL errors
   at the spot where there is a comment about error being expected.

  SIMPLE Tests: - names which start with 's' should analyze or compile cleanly.

These tests are being shared back to industry in hopes of getting together
a joint set of tests, checked out and verified, which we can all use to 
make sure our various VHDL CAD tools work correctly.

Your comments and especially constructive criticism is urgently requested
via any way we can get it.  All replies and resulting changes/updates will
be posted back to the same places these tests were originally posted.

Thanks for your support!

--Steve Grout, MCC CAD Program. (512)338-3516, grout@mcc.com


---- Cut Here and unpack ----
#!/bin/sh
#
# This is a 'shar' archive.  Cut out everything above the line
# and unpack them with /bin/sh, i.e., using a command like:
#     % sh < {the contents of this message after cutting}
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echo "--------------------------------------------------"
echo "Starting to extract Chapter 01 of a 1076-1987 VHDL"
echo "    translated DoD/Intermetrics test suite...."
echo "--------------------------------------------------"
echo x - TEST-SYNOPSIS.text
sed 's/^X//' >TEST-SYNOPSIS.text <<'*-*-END-of-TEST-SYNOPSIS.text-*-*'
X------------------------------------------------------------------------
XChapter: 01-DesignEntity
X------------------------------------------------------------------------
X
X------------------------------------------------------------------------
XParagraph: Interface Declarations to Entity declarations - 1.1 --> 1.1
X------------------------------------------------------------------------
XTest:      e-01-1-0-0001a.vhdl
X-- Check that the order <key words and entity_declarative_
X-- may not be varied.
XTest:      e-01-1-0-0002a.vhdl
X-- Check that if the design entity name is given at the end of the interface
X-- declaration it must be the same as the obligatory name at the beginning of
X-- the interface declaration.
XTest:      s-01-1-0-0001a.vhdl
X-- Check that the design entity name is optional at the end of the interface
X-- and begin is optional.
X
X------------------------------------------------------------------------
XParagraph: Ports - 1.1.1 --> 1.1.1.2
X------------------------------------------------------------------------
XTest:      e-01-1-1-0001a.vhdl
X-- Check order of generic and port clauses are correct.
XTest:      e-01-1-1-0002a.vhdl
X-- Check that the only object class permitted in a formal generic list is
X-- "constant".
XTest:      e-01-1-1-0003a.vhdl
X-- Check that the only mode permitted in a formal generic list is "in".
XTest:      e-01-1-1-0004a.vhdl
X-- Check that when no object class is explicitly specicfied " constant" is
X-- assumed.
XTest:      e-01-1-1-0005a.vhdl
X-- Check that the only object class permitted in a formal port list is 
X-- "signal".
XTest:      e-01-1-1-0006a.vhdl
X-- Check that a formal port of mode "in" is permitted only to have a 
X-- corresponding actual port which is a local signal or a port of mode "in", 
X-- "inout", or "buffer".
XTest:      e-01-1-1-0007a.vhdl
X-- Check that a formal port of mode "OUT" is permitted only to have a 
X-- corresponding actual port which is a local signal or a port of mode "OUT", 
X-- "inout".
XTest:      e-01-1-1-0008a.vhdl
X-- Check that a formal port of mode "buffer" is permitted only to have a 
X-- corresponding actual port which is a local signal or a port of mode 
X-- "buffer".
XTest:      e-01-1-1-0009a.vhdl
X-- Check that a formal port of mode "inout" is permitted only to have a 
X-- corresponding actual port which is a local signal or a port of mode 
X-- "inout".
XTest:      e-01-1-1-0010a.vhdl
X-- Check that if the actual port which corresponds to formal port of mode
X-- "buffer" is a signal then that signal must not be otherwise updated.
XTest:      e-01-1-1-0011a.vhdl
X-- Check that all signals which are actual ports corresponding to formal
X-- ports must be denoted by a static name.
XTest:      e-01-1-1-0012a.vhdl
X--	Check that unconnected ports of mode "out", "inout", buffer,
X--      and "linkage" must not be of an unconstrained array type.
XTest:      e-01-1-1-0013a.vhdl
X--	Check that unconnected ports of mode "in" with no default
X--	expression must not be an unconstrainded array.
XTest:      s-01-1-1-0001a.vhdl
X-- Check that formal port lists and formal generic lists are optional in
X-- interface declarations.
XTest:      s-01-1-1-0002a.vhdl
X-- Check that explicit specification of mode is optional in a formal generic
X-- list.
XTest:      s-01-1-1-0003a.vhdl
X-- Check that when no object class is explicitly specified, "signal" is assumed.
XTest:      s-01-1-1-0004a.vhdl
X-- Check that the actual corresponding to a formal port of any mode may be 
X-- the reserved word "open".
XTest:      s-01-1-1-0005a.vhdl
X-- Check that a formal port of mode "linkage" is permitted only to have a 
X-- corresponding actual port which is a signal or a port of any mode.
X-- The formal ports are contained in the port association list of the component
X-- COM_1. The actuals, with the variety of permitted modes are declared
X-- in the entity port list and a signal decl'd in the block. The test
X-- occurs in the analysis of the component instantiation stm.
XTest:      s-01-1-1-0006a.vhdl
X--	Check that connected ports of mode "in", "out", "buffer", "inout",
X--      and "linkage" may be of an unconstrained array type. 
X
X------------------------------------------------------------------------
X  Paragraph: Generics - 1.1.2 --> 1.1.1.1
X------------------------------------------------------------------------
X    tests:
X
X------------------------------------------------------------------------
X  Paragraph: Interface Declaration Part to Entity Declarative Part - 1.1.3 --> 1.1.2
X------------------------------------------------------------------------
XTest:      e-01-1-2-0001a.vhdl
X-- Check that entity, body, and  component
X-- are not permitted in an entity declaration.
XTest:      e-01-1-2-0002a.vhdl
X-- Check that signal and variable declarations are not permitted in an interface
X-- description.
XTest:      s-01-1-2-0002a.vhdl
X-- Check that type, subtype, alias, constant, and attribute
X-- declarations, attribute specifications, subprogram declarations, subprogram
X-- body, signal declarations, file declarations, disconnection specifications
X-- and use statements are allowed  in the entity declarative part.
X
X------------------------------------------------------------------------
X  Paragraph: Entity Statement Part - --> 1.1.3
X------------------------------------------------------------------------
XTest:      e-01-1-3-0001a.vhdl
X-- Checks that non-passive entity statement items are not allowed.
XTest:      s-01-1-3-0001a.vhdl
X-- Check that concurrent assertion statements, passive concurrent procedure
X-- calls, and passive process statements are allowed in an entity statement.
X
X------------------------------------------------------------------------
X  Paragraph: Body Declarations to Architectural and Configuration declarations - 1.2 -->
X------------------------------------------------------------------------
X    tests:
X
X------------------------------------------------------------------------
X  Paragraph: Architectural Body Declarations - 1.2.1 --> 1.2
X------------------------------------------------------------------------
XTest:      e-01-2-0-0001a.vhdl
X-- Check that a body declaration must be associated with an existing interface
X-- declaration.
XTest:      e-01-2-0-0002a.vhdl
X-- Check that if the body name is given at the end of the body declaration it
X-- must be the same as the obligatory name at the beginning of the body
X-- declaration.
XTest:      e-01-2-0-0003a.vhdl
X-- Checks that all key words are required in an architectural body.
XTest:      s-01-2-0-0001a.vhdl
X-- Check that an interface declaration may have one or more bodies associated
X-- with it.
XTest:      s-01-2-0-0002a.vhdl
X-- Check that the body name at the end of the body declaration is optional.
X
X------------------------------------------------------------------------
X  Paragraph: Architectural Declaration Part - --> 1.2.1
X------------------------------------------------------------------------
XTest:      e-01-2-1-0001a.vhdl
X-- Check that entities and bodies are not allowed in the
X-- architecture declarative part.
XTest:      s-01-2-1-0001a.vhdl
X-- contain: subprogram declaration, subprogram body, type declaration,
X-- subtype declaration, constant declaration, signal declaration, file
X-- declaration, alias declaration, component declaration, attribute
X-- declaration, attribute specification, configuration declaration,
X-- disconnection specification, or use clause.
X
X------------------------------------------------------------------------
X  Paragraph: Architectural Statement Part -  --> 1.2.2
X------------------------------------------------------------------------
XTest:      e-01-2-2-0001a.vhdl
X-- Check that sequential statements: null, IF, case, loop, and procedure
X-- call statements are not permitted  are not allowed in a architecture
X-- statement.
XTest:      s-01-2-2-0001a.vhdl
X-- Check that concurrent signal assignment, concurrent assertion, generate,
X-- and component instantiation statements are permitted in a set of
X-- statements.  Check that concurrent assertion statements which are
X-- indisguishable from assertion statements and concurrent signal assignment
X-- statements which are indistinguishable from signal assignment statements are
X-- also permitted.
X
X------------------------------------------------------------------------
X  Paragraph: Configuration Body Declarations to Configuration Declarations - 1.2.2 --> 1.3
X------------------------------------------------------------------------
XTest:      e-01-3-0-0001a.vhdl
X-- Check that if the body name is given at the end of the configuration
X-- body declaration it must be the same as the obligatory name at the 
X-- beginning of the declaration.
X
X------------------------------------------------------------------------
X  Paragraph: Block Configuration - --> 1.3.1
X------------------------------------------------------------------------
X
X------------------------------------------------------------------------
X  Paragraph: Component Configuration - --> 1.3.2
X------------------------------------------------------------------------
*-*-END-of-TEST-SYNOPSIS.text-*-*
echo x - e-01-1-0-0001a.vhdl
sed 's/^X//' >e-01-1-0-0001a.vhdl <<'*-*-END-of-e-01-1-0-0001a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X	--
X	--		Copyright Intermetrics 1986
X	--
X	-- 	This material may be reproduced by or for the 
X	--      U.S. Government pursuant to the copyright license 
X	-- 	under DAR clause 7-104.9(a) (1981 May)
X	--
X	--
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-01-1-0-0001A.VHDL
X-- Version: %W% - last modified %E%
X-- sccsid:  -- %G% %W% --
X-- Description:
X-- Check that the order <key words and entity_declarative_
X-- may not be varied.
X-- ADO 05/18/88
X-- 
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)Ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E0  is                         --should be error-free
X    port (B:BIT);
X    begin
X	 assert B='1';
Xend E0;
X
Xentity E1  port (B:BIT) is       -- SYNTAX ERROR: unidentified expression
X                                 -- (port list out of sequence)
Xend E1;
X
Xentity E2  is
X    begin
X	assert B='1';
X    port (B:BIT);               --SYNTAX ERROR: port list out of sequence
Xend E2;
X
Xentity E3 is
X    port (B:BIT)
X    begin ;                      --SYNTAX ERROR: missing end statement.
*-*-END-of-e-01-1-0-0001a.vhdl-*-*
echo x - e-01-1-0-0002a.vhdl
sed 's/^X//' >e-01-1-0-0002a.vhdl <<'*-*-END-of-e-01-1-0-0002a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X	--
X	--		Copyright Intermetrics 1986
X	--
X	-- 	This material may be reproduced by or for the 
X	--      U.S. Government pursuant to the copyright license 
X	-- 	under DAR clause 7-104.9(a) (1981 May)
X	--
X	--
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-01-1-0-0002A.VHDL
X-- Version: %W% - last modified %E%
X-- sccsid:  -- %G% %W% --
X-- Description:
X-- Check that if the design entity name is given at the end of the interface
X-- declaration it must be the same as the obligatory name at the beginning of
X-- the interface declaration.
X-- ADO 05/18/88
X-- 
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)Ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E1  is
X    port (B:BIT) ;
Xend E2;      --SYNTAX ERROR: entity name in end statement does not match
X             --   entity name in entity statement
X
X
*-*-END-of-e-01-1-0-0002a.vhdl-*-*
echo x - e-01-1-1-0001a.vhdl
sed 's/^X//' >e-01-1-1-0001a.vhdl <<'*-*-END-of-e-01-1-1-0001a.vhdl-*-*'
X-- /* -*- Mode: vhdl; -*-  */
X-- ************************************************************************
X--  Copyright (C) 1988 Microelectronics and Computer Technology Corporation
X--  - VLSI CAD Program - %Y%
X-- ************************************************************************
X--  File Contents:  Tests For IEEE 1076-1987 VHDL
X--  This file may be redistributed provided the above copyright notice 
X--  appears on all copies and that the further free redistribution of this 
X--  file is not in any way restricted by those who redistribute it.
X--
X--  These VHDL tests are distributed 'as is', without warranties of any kind.
X--
X--  This file is not part of any MCC proprietary or DoD VHDL software.
X-- 
X--     File:       %P%
X--     Author:     Deene Ogden
X--     Version:    %W% - last modified %E%
X--     sccsid:     -- %G% %W% --
X--     Description:
X-- Check order of generic and port clauses are correct.
X-- 	
X--     Modification History
X--   --------------------------------------------------------------------
X-- 
X-- **********************************************************************
X-- 
X-- Begin test: >>>
X
Xentity E is                       -- correct order
X	generic (N:natural:= 2);
X	port (B:BIT);
Xend E;
X
Xentity E1 is                       -- ERROR incorrect order
X	port (B:BIT);
X	generic (N:natural:= 2);
X	
Xend E1;
X
*-*-END-of-e-01-1-1-0001a.vhdl-*-*
echo x - e-01-1-1-0002a.vhdl
sed 's/^X//' >e-01-1-1-0002a.vhdl <<'*-*-END-of-e-01-1-1-0002a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X	--
X	--		Copyright Intermetrics 1986
X	--
X	-- 	This material may be reproduced by or for the 
X	--      U.S. Government pursuant to the copyright license 
X	-- 	under DAR clause 7-104.9(a) (1981 May)
X	--
X	--
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-01-1-1-0002A.VHDL
X-- Version: %W% - last modified %E%
X-- sccsid:  -- %G% %W% --
X-- Description:
X-- Check that the only object class permitted in a formal generic list is
X-- "constant".
X-- ADO 05/18/88
X-- 
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)Ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is 
X  generic ( variable C : integer;
X-- ERROR: only object class allowed in a generic list "constant".
X            signal S1 : boolean)
X-- ERROR: only object class allowed in a generic list "constant".
Xend E;
*-*-END-of-e-01-1-1-0002a.vhdl-*-*
echo x - e-01-1-1-0003a.vhdl
sed 's/^X//' >e-01-1-1-0003a.vhdl <<'*-*-END-of-e-01-1-1-0003a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X	--
X	--		Copyright Intermetrics 1986
X	--
X	-- 	This material may be reproduced by or for the 
X	--      U.S. Government pursuant to the copyright license 
X	-- 	under DAR clause 7-104.9(a) (1981 May)
X	--
X	--
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-01-1-1-0003A.VHDL
X-- Version: %W% - last modified %E%
X-- sccsid:  -- %G% %W% --
X-- Description:
X-- Check that the only mode permitted in a formal generic list is "in".
X-- ADO 05/15/88
X-- 
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)Ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
X generic ( C : inout Bit;
X -- ERROR: only mode permitted in a formal generic list is "in"
X           D : out Bit;
X -- ERROR: only mode permitted in a formal generic list is "in"
X           E : linkage BIT;
X -- ERROR: only mode permitted in a formal generic list is "in"
X           F : buffer BIT)
X -- ERROR: only mode permitted in a formal generic list is "in"
Xend E;
*-*-END-of-e-01-1-1-0003a.vhdl-*-*
echo x - e-01-1-1-0004a.vhdl
sed 's/^X//' >e-01-1-1-0004a.vhdl <<'*-*-END-of-e-01-1-1-0004a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X	--
X	--		Copyright Intermetrics 1986
X	--
X	-- 	This material may be reproduced by or for the 
X	--      U.S. Government pursuant to the copyright license 
X	-- 	under DAR clause 7-104.9(a) (1981 May)
X	--
X	--
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-01-1-1-0004A.VHDL
X-- Version: %W% - last modified %E%
X-- sccsid:  -- %G% %W% --
X-- Description:
X-- Check that when no object class is explicitly specicfied " constant" is
X-- assumed.
X-- ADO 05/15/88
X-- 
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)Ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
X    generic  (G1: boolean; G2 : integer) ;
Xend E;
X
Xarchitecture AB of E is
X-- L_X_1: block
X begin
X  process
X  begin
X    G1 := true;
X    -- ERROR: with no object class "constant" is assumed and constants
X    -- cannot be changed
X    G2 := 5;
X    -- ERROR: with no object class "constant" is assumed and constants
X    -- cannot be changed
X  end process;
X--  end block;
Xend AB;
*-*-END-of-e-01-1-1-0004a.vhdl-*-*
echo x - e-01-1-1-0005a.vhdl
sed 's/^X//' >e-01-1-1-0005a.vhdl <<'*-*-END-of-e-01-1-1-0005a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X	--
X	--		Copyright Intermetrics 1986
X	--
X	-- 	This material may be reproduced by or for the 
X	--      U.S. Government pursuant to the copyright license 
X	-- 	under DAR clause 7-104.9(a) (1981 May)
X	--
X	--
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-01-1-1-0005A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid:  -- %G% %W% --
X-- Description:
X-- Check that the only object class permitted in a formal port list is 
X-- "signal".
X-- ADO 05/18/88
X-- 
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)Ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E1  is 
X    port (variable C1 : inout integer) ;
X    --ERROR: only an object class of signal is allowed in a formal port list.
Xend E1;
X
Xentity E2  is
X    port (constant CT : out integer) ;
X    --ERROR: only an object class of signal is allowed in a formal port list.
Xend E2;
*-*-END-of-e-01-1-1-0005a.vhdl-*-*
echo x - e-01-1-1-0006a.vhdl
sed 's/^X//' >e-01-1-1-0006a.vhdl <<'*-*-END-of-e-01-1-1-0006a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X	--
X	--		Copyright Intermetrics 1986
X	--
X	-- 	This material may be reproduced by or for the 
X	--      U.S. Government pursuant to the copyright license 
X	-- 	under DAR clause 7-104.9(a) (1981 May)
X	--
X	--
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-01-1-1-0006A.VHDL
X-- Version: %W% - last modified %E%
X-- sccsid:  -- %G% %W% --
X-- Description:
X-- Check that a formal port of mode "in" is permitted only to have a 
X-- corresponding actual port which is a local signal or a port of mode "in", 
X-- "inout", or "buffer".
X-- ADO 05/18/88
X-- 
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)Ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E  is
X    port (w : in BIT;
X	  x : inout BIT;
X	  y : buffer BIT;
X	  z : out BIT;
X          q : linkage BIT) ;
Xend E;
X
X
Xarchitecture AB of E is
X-- L_X_1: block
X  
X    component COM_1 port(A,B,C,D,E : in BIT) ;
X	end component;
X
X begin
X
X    --ERROR: a formal port of mode "in" is not allowed to be mapped to a actual
X    --       port of mode out.
X
X	CIS1 : COM_1 port map (w, x, y, z, q );
X	CIS2 : COM_1 port map (A => w, B => x, C => y, D => z, E => q );
X
X--  end block;
Xend AB;
*-*-END-of-e-01-1-1-0006a.vhdl-*-*
echo x - e-01-1-1-0007a.vhdl
sed 's/^X//' >e-01-1-1-0007a.vhdl <<'*-*-END-of-e-01-1-1-0007a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X	--
X	--		Copyright Intermetrics 1986
X	--
X	-- 	This material may be reproduced by or for the 
X	--      U.S. Government pursuant to the copyright license 
X	-- 	under DAR clause 7-104.9(a) (1981 May)
X	--
X	--
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-01-1-1-0007A.VHDL
X-- Version: %W% - last modified %E%
X-- sccsid:  -- %G% %W% --
X-- Description:
X-- Check that a formal port of mode "OUT" is permitted only to have a 
X-- corresponding actual port which is a local signal or a port of mode "OUT", 
X-- "inout".
X-- ADO 05/18/88
X-- 
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)Ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E  is
X    port (v : out BIT;
X	  w : inout BIT;
X	  x : in  BIT;
X	  y : buffer BIT;
X	  z : linkage BIT ) ;
Xend E;
X
Xarchitecture AB of E is
X-- L_X_1: block
X  
X    component COM_1 port (A,B,C,D,E : out BIT) ;
X	end component;
X
X begin
X    -- No Errors should be flagged for the first 2 associations in the
X    -- component instantiation stms
X
X    --ERROR: a formal port of mode "out" is not allowed to be mapped to a actual
X    --       port of mode "in" (association for C)
X
X    --ERROR: a formal port of mode "out" is not allowed to be mapped to a actual
X    --       port of mode "buffer" (association for D)
X
X    --ERROR: a formal port of mode "out" is not allowed to be mapped to a actual
X    --       port of mode "linkage" (association for E)
X
X	CIS1 : COM_1 port map (v, w, x, y, z );
X	CIS2 : COM_1 port map (A => v, B => w, C => x, D => y, E => z );
X
X--  end block;
Xend AB;
*-*-END-of-e-01-1-1-0007a.vhdl-*-*
echo x - e-01-1-1-0008a.vhdl
sed 's/^X//' >e-01-1-1-0008a.vhdl <<'*-*-END-of-e-01-1-1-0008a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X	--
X	--		Copyright Intermetrics 1986
X	--
X	-- 	This material may be reproduced by or for the 
X	--      U.S. Government pursuant to the copyright license 
X	-- 	under DAR clause 7-104.9(a) (1981 May)
X	--
X	--
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-01-1-1-0008A.VHDL
X-- Version: %W% - last modified %E%
X-- sccsid:  -- %G% %W% --
X-- Description:
X-- Check that a formal port of mode "buffer" is permitted only to have a 
X-- corresponding actual port which is a local signal or a port of mode 
X-- "buffer".
X-- ADO 05/18/88
X-- 
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)Ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E  is
X    port (v : out BIT;
X	  w : inout BIT;
X	  x : in  BIT;
X	  y : buffer BIT;
X	  z : linkage BIT ) ;
Xend E;
X
Xarchitecture AB of E is
X-- L_X_1: block
X  
X    component COM_1 port(A,B,C,D,E : buffer  BIT) ;
X	end component;
X
X begin
X
X    --ERROR: a formal port of mode "buffer" is not allowed to be mapped 
X    --       to a actual port of mode "out" (association for A)
X
X    --ERROR: a formal port of mode "buffer" is not allowed to be mapped to 
X    --       port of mode "inout" (association for B)
X
X    --ERROR: a formal port of mode "buffer" is not allowed to be mapped to 
X    --       port of mode "in" (association for C)
X
X    --ERROR: a formal port of mode "buffer" is not allowed to be mapped to 
X    --       port of mode "linkage" (association for E)
X
X	CIS1 : COM_1 port map (v, w, x, y, z );
X	CIS2 : COM_1 port map (A => v, B => w, C => x, D => y, E => z );
X
X--  end block;
Xend AB;
*-*-END-of-e-01-1-1-0008a.vhdl-*-*
echo x - e-01-1-1-0009a.vhdl
sed 's/^X//' >e-01-1-1-0009a.vhdl <<'*-*-END-of-e-01-1-1-0009a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X	--
X	--		Copyright Intermetrics 1986
X	--
X	-- 	This material may be reproduced by or for the 
X	--      U.S. Government pursuant to the copyright license 
X	-- 	under DAR clause 7-104.9(a) (1981 May)
X	--
X	--
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-01-1-1-0009A.VHDL
X-- Version: %W% - last modified %E%
X-- sccsid:  -- %G% %W% --
X-- Description:
X-- Check that a formal port of mode "inout" is permitted only to have a 
X-- corresponding actual port which is a local signal or a port of mode 
X-- "inout".
X-- ADO 05/18/88
X-- 
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)Ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E  is
X    port (v : out BIT;
X	  w : inout BIT;
X	  x : in  BIT;
X	  y : buffer BIT;
X	  z : linkage BIT) ;
Xend E;
X
Xarchitecture AB of E is
X-- L_X_1: block
X  
X    component COM_1 port(A,B,C,D,E : inout BIT) ;
X	end component;
X
X begin
X
X    --ERROR: a formal port of mode "inout" is not allowed to be mapped 
X    --       to a actual port of mode "out" (association for A)
X
X    --ERROR: a formal port of mode "inout" is not allowed to be mapped to 
X    --       port of mode "in" (association for C)
X
X    --ERROR: a formal port of mode "buffer" is not allowed to be mapped to 
X    --       port of mode "buffer" (association for D)
X
X    --ERROR: a formal port of mode "buffer" is not allowed to be mapped to 
X    --       port of mode "linkage" (association for E)
X
X	CIS1 : COM_1 port map (v, w, x, y, z );
X	CIS2 : COM_1 port map (A => v, B => w, C => x, D => y, E => z );
X
X--  end block;
Xend AB;
*-*-END-of-e-01-1-1-0009a.vhdl-*-*
echo x - e-01-1-1-0010a.vhdl
sed 's/^X//' >e-01-1-1-0010a.vhdl <<'*-*-END-of-e-01-1-1-0010a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X	--
X	--		Copyright Intermetrics 1986
X	--
X	-- 	This material may be reproduced by or for the 
X	--      U.S. Government pursuant to the copyright license 
X	-- 	under DAR clause 7-104.9(a) (1981 May)
X	--
X	--
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-01-1-1-0010A.VHDL
X-- Version: %W% - last modified %E%
X-- sccsid:  -- %G% %W% --
X-- Description:
X-- Check that if the actual port which corresponds to formal port of mode
X-- "buffer" is a signal then that signal must not be otherwise updated.
X-- ADO 05/18/88
X-- 
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)Ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E  is
X    port ( PT : buffer integer) ;
Xend E;
X
Xarchitecture AB of E is
X-- L_X_1: block
X  
X    component COM_1 port(X: buffer integer);
X	end component;
X
X begin
X  CIS1 : COM_1 port map (PT);
X  CIS2 : COM_1 port map (X => PT);
X		
X  PP: process
X  begin
X    PT <= 5 ;
X    -- ERROR Signal of mode buffer must not be updated.-- ~r ??
X  end process PP;
X--  end block;
Xend AB;
*-*-END-of-e-01-1-1-0010a.vhdl-*-*
echo x - e-01-1-1-0011a.vhdl
sed 's/^X//' >e-01-1-1-0011a.vhdl <<'*-*-END-of-e-01-1-1-0011a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X	--
X	--		Copyright Intermetrics 1986
X	--
X	-- 	This material may be reproduced by or for the 
X	--      U.S. Government pursuant to the copyright license 
X	-- 	under DAR clause 7-104.9(a) (1981 May)
X	--
X	--
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-01-1-1-0011A.VHDL
X-- Version: %W% - last modified %E%
X-- sccsid:  -- %G% %W% --
X-- Description:
X-- Check that all signals which are actual ports corresponding to formal
X-- ports must be denoted by a static name.
X-- ADO 05/18/88
X-- 
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)Ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xpackage int_entity_types is
X    type ar_sig_range is range 1 to 8;
X    type ar_signal is array (ar_sig_range) of BIT;	
Xend int_entity_types ;
X
Xuse int_entity_types.all; 
Xentity E  is
X    port (iface_array : ar_signal;
X    	  iface_index : ar_sig_range) ;
Xend E;
X
Xarchitecture AB of E is
X-- L_X_1: block
X   component COM_1 port ( F1 : in BIT);
X	end component;
X   
X begin
X    --ERROR: signal must be denoted by static names
X    CIS1: COM_1 port map ( iface_array (iface_index)); 
X--  end block ;
Xend AB;
*-*-END-of-e-01-1-1-0011a.vhdl-*-*
echo x - e-01-1-1-0012a.vhdl
sed 's/^X//' >e-01-1-1-0012a.vhdl <<'*-*-END-of-e-01-1-1-0012a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X	--
X	--		Copyright Intermetrics 1986
X	--
X	-- 	This material may be reproduced by or for the 
X	--      U.S. Government pursuant to the copyright license 
X	-- 	under DAR clause 7-104.9(a) (1981 May)
X	--
X	--
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-01-1-1-0012.VHDL
X-- Version: %W% - last modified %E%
X-- sccsid:  -- %G% %W% --
X-- Description:
X--	Check that unconnected ports of mode "out", "inout", buffer,
X--      and "linkage" must not be of an unconstrained array type.
X-- ADO 05/18/88
X-- 
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)Ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
X    entity ee1a is
X    	type arr_unconstrain is array (POSITIVE range <>) OF BIT;
X    end ee1a;
X
X    architecture Bee1a of ee1a is
X--     X: block
X    	component c port (c1 : out arr_unconstrain;
X    			  c2 : inout arr_unconstrain;
X    			  c3 : buffer arr_unconstrain;
X    			  c4 : linkage  arr_unconstrain);
X	end component;
X    	begin
X    	  CIS1 : c port map (open, open, open, open);
X    	  CIS2 : c port map (c1 => open, c2 => open, c3 => open, c4 => open);
X--     	end block;
X    end Bee1a;
*-*-END-of-e-01-1-1-0012a.vhdl-*-*
echo x - e-01-1-1-0013a.vhdl
sed 's/^X//' >e-01-1-1-0013a.vhdl <<'*-*-END-of-e-01-1-1-0013a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X	--
X	--		Copyright Intermetrics 1986
X	--
X	-- 	This material may be reproduced by or for the 
X	--      U.S. Government pursuant to the copyright license 
X	-- 	under DAR clause 7-104.9(a) (1981 May)
X	--
X	--
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-01-1-1-00013A.VHDL
X-- Version: %W% - last modified %E%
X-- sccsid:  -- %G% %W% --
X-- Description:
X--	Check that unconnected ports of mode "in" with no default
X--	expression must not be an unconstrainded array.
X-- ADO 05/18/88
X-- 
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)Ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity ee11 is
X	type arr_unconstrain is array (POSITIVE range <>) OF BIT;
Xend ee11;
X
Xarchitecture abee11 of ee11 is
X-- DDD: block
X	component C port (C1 : in arr_unconstrain );	
X	end component;
X   begin
X	CIS1 : C port map (open);
X	CIS2 : C port map (C1 => open);   
X--    end block ;
Xend abee11;
*-*-END-of-e-01-1-1-0013a.vhdl-*-*
echo x - e-01-1-2-0001a.vhdl
sed 's/^X//' >e-01-1-2-0001a.vhdl <<'*-*-END-of-e-01-1-2-0001a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X	--
X	--		Copyright Intermetrics 1986
X	--
X	-- 	This material may be reproduced by or for the 
X	--      U.S. Government pursuant to the copyright license 
X	-- 	under DAR clause 7-104.9(a) (1981 May)
X	--
X	--
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-01-1-2-0001A.VHDL
X-- Version: %W% - last modified %E%
X-- sccsid:  -- %G% %W% --
X-- Description:
X-- Check that entity, body, and  component
X-- are not permitted in an entity declaration.
X-- ADO 05/20/88
X-- 
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)Ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E3 is
X     entity E2 is
X      --ERROR: ENTITY are not allowed in an entity decalaration
X     end E2;
Xend E3;
X
X
X
Xentity E4 is
X     architecture AB of E is
X      --ERROR: architecture body are not allowed in an entity decalaration
X--L_X_1:     block
X     begin
X     process
X     begin
X     null;
X     end process;
X--     end block;
X     end AB;
Xend E4;
X
X
Xentity E5 is
X     component COMP port (A:in BIT);
X      --ERROR: component statements are not allowed in an entity decalaration
Xend E5;
X
*-*-END-of-e-01-1-2-0001a.vhdl-*-*
echo x - e-01-1-2-0002a.vhdl
sed 's/^X//' >e-01-1-2-0002a.vhdl <<'*-*-END-of-e-01-1-2-0002a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X	--
X	--		Copyright Intermetrics 1986
X	--
X	-- 	This material may be reproduced by or for the 
X	--      U.S. Government pursuant to the copyright license 
X	-- 	under DAR clause 7-104.9(a) (1981 May)
X	--
X	--
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-01-1-2-0002A.VHDL
X-- Version: %W% - last modified %E%
X-- sccsid:  -- %G% %W% --
X-- Description:
X-- Check that signal and variable declarations are not permitted in an interface
X-- description.
X-- ADO 05/20/88
X-- 
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)Ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E2  is
X    port  (A:BIT; B:out BIT);
X    variable V:INTEGER;    --SEMANTICS ERROR: variable cannot be declared in 
Xend E2;                    --   an entity.
X
*-*-END-of-e-01-1-2-0002a.vhdl-*-*
echo x - e-01-1-3-0001a.vhdl
sed 's/^X//' >e-01-1-3-0001a.vhdl <<'*-*-END-of-e-01-1-3-0001a.vhdl-*-*'
X-- /* -*- Mode: vhdl; -*-  */
X-- ************************************************************************
X--  Copyright (C) 1988 Microelectronics and Computer Technology Corporation
X--  - VLSI CAD Program - %Y%
X-- ************************************************************************
X--  File Contents:  Tests For IEEE 1076-1987 VHDL
X--  This file may be redistributed provided the above copyright notice 
X--  appears on all copies and that the further free redistribution of this 
X--  file is not in any way restricted by those who redistribute it.
X--
X--  These VHDL tests are distributed 'as is', without warranties of any kind.
X--
X--  This file is not part of any MCC proprietary or DoD VHDL software.
X-- 
X--     File:       %P%
X--     Author:     Deene Ogden
X--     Version:    %W% - last modified %E%
X--     sccsid:     -- %G% %W% --
X--     Description:
X-- Checks that non-passive entity statement items are not allowed.
X-- 	
X--     Modification History
X--   --------------------------------------------------------------------
X-- 
X-- **********************************************************************
X-- Begin test: >>>
X
Xentity E is
X port (A: in BIT;
X       B: out BIT);
X procedure P is
X  signal A = '1';         -- disallowed signal assignement for subsequent
X			  -- passive procedure call
X  begin
X    return;
X end P;
X
X begin
X  P;			  -- ERROR, non-passive procedure being called
X
X  process
X   begin
X     signal B = '1';      -- ERROR, non-passive process being used
X  end process;
X
Xend E;
X
*-*-END-of-e-01-1-3-0001a.vhdl-*-*
echo x - e-01-2-0-0001a.vhdl
sed 's/^X//' >e-01-2-0-0001a.vhdl <<'*-*-END-of-e-01-2-0-0001a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X	--
X	--		Copyright Intermetrics 1986
X	--
X	-- 	This material may be reproduced by or for the 
X	--      U.S. Government pursuant to the copyright license 
X	-- 	under DAR clause 7-104.9(a) (1981 May)
X	--
X	--
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-01-2-0-0001A.VHDL
X-- Version: %W% - last modified %E%
X-- sccsid:  -- %G% %W% --
X-- Description:
X-- Check that a body declaration must be associated with an existing interface
X-- declaration.
X-- ADO 05/24/88
X-- 
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)Ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xarchitecture B1 of missing_interface is    --SEMANTICS ERROR: entity E2 is unknown
X-- L_X_1: block
X begin
X  process
X  begin
X    null;
X  end process;
X--  end block;
Xend B1;
X
*-*-END-of-e-01-2-0-0001a.vhdl-*-*
echo x - e-01-2-0-0002a.vhdl
sed 's/^X//' >e-01-2-0-0002a.vhdl <<'*-*-END-of-e-01-2-0-0002a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X	--
X	--		Copyright Intermetrics 1986
X	--
X	-- 	This material may be reproduced by or for the 
X	--      U.S. Government pursuant to the copyright license 
X	-- 	under DAR clause 7-104.9(a) (1981 May)
X	--
X	--
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-01-2-0-0002A.VHDL
X-- Version: %W% - last modified %E%
X-- sccsid:  -- %G% %W% --
X-- Description:
X-- Check that if the body name is given at the end of the body declaration it
X-- must be the same as the obligatory name at the beginning of the body
X-- declaration.
X-- ADO 05/24/88
X-- 
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)Ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E1  is
X    port (B:BIT) ;
Xend E1;
X
Xarchitecture B1 of E1 is
X-- L_X_1: block
X begin
X  process
X  begin
X    null;
X  end process;
X-- end block;
Xend B2;     --SYNTAX ERROR: body name in end statement does not match name in
X            --   body declaration statement
X
*-*-END-of-e-01-2-0-0002a.vhdl-*-*
echo x - e-01-2-0-0003a.vhdl
sed 's/^X//' >e-01-2-0-0003a.vhdl <<'*-*-END-of-e-01-2-0-0003a.vhdl-*-*'
X-- /* -*- Mode: vhdl; -*-  */
X-- ************************************************************************
X--  Copyright (C) 1988 Microelectronics and Computer Technology Corporation
X--  - VLSI CAD Program - %Y%
X-- ************************************************************************
X--  File Contents:  Tests For IEEE 1076-1987 VHDL
X--  This file may be redistributed provided the above copyright notice 
X--  appears on all copies and that the further free redistribution of this 
X--  file is not in any way restricted by those who redistribute it.
X--
X--  These VHDL tests are distributed 'as is', without warranties of any kind.
X--
X--  This file is not part of any MCC proprietary or DoD VHDL software.
X-- 
X--     File:       %P%
X--     Author:     Deene Ogden
X--     Version:    %W% - last modified %E%
X--     sccsid:     -- %G% %W% --
X--     Description:
X-- Checks that all key words are required in an architectural body.
X-- 	
X--     Modification History
X--   --------------------------------------------------------------------
X-- 
X-- **********************************************************************
X-- Begin test: >>>
X
Xentity E1 is
Xend E1;
X
Xarchitecture T1 of E1
X  begin                     -- ERROR - missing "is" keyword
X   process
X     begin;
X   end process;
Xend T1;
X
Xarchitecture T2 of E1 is
Xend T2;                     -- ERROR - missing "begin" keyword
X
Xarchitecture T3 of E1 is
X  begin
X    process
X      begin;
X    end process;
X
Xarchitecture T4 of E1 is      -- error-free
X  begin       
X   process
X     begin;
X   end process;
Xend T4;
X  
*-*-END-of-e-01-2-0-0003a.vhdl-*-*
echo x - e-01-2-1-0001a.vhdl
sed 's/^X//' >e-01-2-1-0001a.vhdl <<'*-*-END-of-e-01-2-1-0001a.vhdl-*-*'
X---------------------------------------------------------------------------
X--
X--
X---------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-01-2-1-0001A.VHDL
X-- Version: %W% - last modified %E%
X-- sccsid:  -- %G% %W% --
X-- Description:
X-- Check that entities and bodies are not allowed in the
X-- architecture declarative part.
X-- ADO 05/25/88
X-- 
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)Ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
Xend;
X
Xarchitecture A of E is
X
Xentity B is             -- ERROR - entity not allowed here
Xend;
X
Xarchitecture B of E is  -- ERROR - architecture not allowed here
Xbegin
Xend B;
X
Xbegin
X  process
X    begin
X  end process;
Xend A;
X
*-*-END-of-e-01-2-1-0001a.vhdl-*-*
echo x - e-01-3-0-0001a.vhdl
sed 's/^X//' >e-01-3-0-0001a.vhdl <<'*-*-END-of-e-01-3-0-0001a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X	--
X	--		Copyright Intermetrics 1986
X	--
X	-- 	This material may be reproduced by or for the 
X	--      U.S. Government pursuant to the copyright license 
X	-- 	under DAR clause 7-104.9(a) (1981 May)
X	--
X	--
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-01-3-0-0001A.VHDL
X-- Version: %W% - last modified %E%
X-- sccsid:  -- %G% %W% --
X-- Description:
X-- Check that if the body name is given at the end of the configuration
X-- body declaration it must be the same as the obligatory name at the 
X-- beginning of the declaration.
X-- ADO 06/2/88
X-- 
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)Ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity top is
Xend top;
X
Xarchitecture hat of top is
X-- SS: block
X	begin
X	process
X	  begin
X	     null;
X	end process ;
X--   end block;
Xend hat;
X
Xconfiguration C of top is 
Xfor
X hat
X  use entity top(hat);
Xend for;
Xend C2;
X-- ERROR: name given at the end must be the same as that given beginning.
*-*-END-of-e-01-3-0-0001a.vhdl-*-*
echo x - s-01-1-0-0001a.vhdl
sed 's/^X//' >s-01-1-0-0001a.vhdl <<'*-*-END-of-s-01-1-0-0001a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X	--
X	--		Copyright Intermetrics 1986
X	--
X	-- 	This material may be reproduced by or for the 
X	--      U.S. Government pursuant to the copyright license 
X	-- 	under DAR clause 7-104.9(a) (1981 May)
X	--
X	--
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-01-1-0-0001A.VHDL
X-- Version: %W% - last modified %E%
X-- sccsid:  -- %G% %W% --
X-- Description:
X-- Check that the design entity name is optional at the end of the interface
X-- and begin is optional.
X-- ADO 05/19/88
X-- 
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)Ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E  is
X port (B:BIT);
Xend;
X
Xentity E1 is
X begin
Xend E1;
*-*-END-of-s-01-1-0-0001a.vhdl-*-*
echo x - s-01-1-1-0001a.vhdl
sed 's/^X//' >s-01-1-1-0001a.vhdl <<'*-*-END-of-s-01-1-1-0001a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X	--
X	--		Copyright Intermetrics 1986
X	--
X        --	This material may be reproduced by or for the 
X	--      U.S. Government pursuant to the copyright license 
X	-- 	under DAR clause 7-104.9(a) (1981 May)
X	--
X	--
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-01-1-1-0001A.VHDL
X-- Version: %W% - last modified %E%
X-- sccsid:  -- %G% %W% --
X-- Description:
X-- Check that formal port lists and formal generic lists are optional in
X-- interface declarations.
X-- ADO 05/19/88
X-- 
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)Ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E0 is
Xend E0;
X
Xentity E is
X    generic (DELAY:TIME:=2 ns);
Xend E;
X
Xentity E1 is
X  port (B : BIT);
Xend E1;
*-*-END-of-s-01-1-1-0001a.vhdl-*-*
echo x - s-01-1-1-0002a.vhdl
sed 's/^X//' >s-01-1-1-0002a.vhdl <<'*-*-END-of-s-01-1-1-0002a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X	--
X	--		Copyright Intermetrics 1986
X	--
X	-- 	This material may be reproduced by or for the 
X	--      U.S. Government pursuant to the copyright license 
X	-- 	under DAR clause 7-104.9(a) (1981 May)
X	--
X	--
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-01-1-1-0002A.VHDL
X-- Version: %W% - last modified %E%
X-- sccsid:  -- %G% %W% --
X-- Description:
X-- Check that explicit specification of mode is optional in a formal generic
X-- list.
X-- ADO 05/19/88
X-- 
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)Ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
X generic ( G1 : in Boolean ; G2 :real);
Xend E;
*-*-END-of-s-01-1-1-0002a.vhdl-*-*
echo x - s-01-1-1-0003a.vhdl
sed 's/^X//' >s-01-1-1-0003a.vhdl <<'*-*-END-of-s-01-1-1-0003a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X	--
X	--		Copyright Intermetrics 1986
X	--
X	-- 	This material may be reproduced by or for the 
X	--      U.S. Government pursuant to the copyright license 
X	-- 	under DAR clause 7-104.9(a) (1981 May)
X	--
X	--
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-01-1-1-0003A.VHDL
X-- Version: %W% - last modified %E%
X-- sccsid:  -- %G% %W% --
X-- Description:
X-- Check that when no object class is explicitly specified, "signal" is assumed.
X-- ADO 05/19/88
X-- 
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)Ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
X  port (PT:boolean );
Xend E;
X
Xarchitecture AB of E is
X--ZZ: block
X  component COM port(S :inout boolean);
X  end component;
X  signal Loc_signal : boolean;
X  begin
X   CIS1: COM port map (S => Loc_signal);
X  process
X  begin
X    IF PT'STABLE then
X      return;
X    end IF;
X  end process;
X-- end block;
Xend AB;
*-*-END-of-s-01-1-1-0003a.vhdl-*-*
echo x - s-01-1-1-0004a.vhdl
sed 's/^X//' >s-01-1-1-0004a.vhdl <<'*-*-END-of-s-01-1-1-0004a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X	--
X	--		Copyright Intermetrics 1986
X	--
X	-- 	This material may be reproduced by or for the 
X	--      U.S. Government pursuant to the copyright license 
X	-- 	under DAR clause 7-104.9(a) (1981 May)
X	--
X	--
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-01-1-1-0004A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid:  -- %G% %W% --
X-- Description:
X-- Check that the actual corresponding to a formal port of any mode may be 
X-- the reserved word "open".
X-- ADO 05/19/88
X-- 
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E  is
X(PT: boolean)
Xend E;
X
Xarchitecture AB of E is
X--WW: block
X   component COM_1 port (W : in integer;
X	                 X : linkage integer;
X	   		 Y : buffer integer;
X			 Z : inout integer);
X   end component;
X
X begin
X
X    CIS0: COM_1 port map (open, open, open, open );
X    CIS1: COM_1 port map (W => open,
X                          X => open,
X                          Y => open,
X                          Z => open );
X-- end block;
Xend AB;
*-*-END-of-s-01-1-1-0004a.vhdl-*-*
echo x - s-01-1-1-0005a.vhdl
sed 's/^X//' >s-01-1-1-0005a.vhdl <<'*-*-END-of-s-01-1-1-0005a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X	--
X	--		Copyright Intermetrics 1986
X	--
X	-- 	This material may be reproduced by or for the 
X	--      U.S. Government pursuant to the copyright license 
X	-- 	under DAR clause 7-104.9(a) (1981 May)
X	--
X	--
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-01-1-1-0005A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid:  -- %G% %W% --
X-- Description:
X-- Check that a formal port of mode "linkage" is permitted only to have a 
X-- corresponding actual port which is a signal or a port of any mode.
X-- The formal ports are contained in the port association list of the component
X-- COM_1. The actuals, with the variety of permitted modes are declared
X-- in the entity port list and a signal decl'd in the block. The test
X-- occurs in the analysis of the component instantiation stm.
X-- ADO 05/19/88
X-- 
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E  is
X    port (X : linkage integer;
X	  Y : buffer integer;
X	  Z : inout integer);
Xend E;
X
Xarchitecture AB of E is
X--ZZ: block
X  
X    component COM_1 port(A : linkage integer;
X			 B : linkage integer ;
X                         C : linkage integer ; 
X			 D : linkage integer);
X    end component;
X    signal M : integer;
X begin
X    CIS1: COM_1 port map (A => M, 
X                          B => X, 
X                          C => Y, 
X                          D => Z);
X-- end block;
Xend AB;
X
*-*-END-of-s-01-1-1-0005a.vhdl-*-*
echo x - s-01-1-1-0006a.vhdl
sed 's/^X//' >s-01-1-1-0006a.vhdl <<'*-*-END-of-s-01-1-1-0006a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X	--
X	--		Copyright Intermetrics 1986
X	--
X	-- 	This material may be reproduced by or for the 
X	--      U.S. Government pursuant to the copyright license 
X	-- 	under DAR clause 7-104.9(a) (1981 May)
X	--
X	--
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-01-1-1-0006A.VHDL
X-- Version: %W% - last modified %E%
X-- sccsid:  -- %G% %W% --
X-- Description:
X--	Check that connected ports of mode "in", "out", "buffer", "inout",
X--      and "linkage" may be of an unconstrained array type. 
X-- ADO 05/19/88
X-- 
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xpackage useful_types is
X	type arr_unconstrain is array (POSITIVE range <>) of integer;
Xend useful_types ;
X
Xuse useful_types.all; 
Xentity e111 is
X    port (p1 : in  arr_unconstrain; 	
X	     p2 : out  arr_unconstrain; 	
X             p3 : inout  arr_unconstrain; 	
X	     p4 : buffer  arr_unconstrain; 	
X	     p5 : linkage  arr_unconstrain) ;
Xend e111;
X
Xarchitecture abe111 of e111 is
X--DDD: block
X  	component C port (C1 : in      arr_unconstrain; 	
X			  C2 : out     arr_unconstrain; 	
X			  C3 : inout   arr_unconstrain; 	
X			  C4 : buffer  arr_unconstrain; 	
X			  C5 : linkage arr_unconstrain);
X        end component;
X     begin
X	CIS1 : C port map (C1 => p1, C2 => p2, C3 => p3, C4 => p4, C5 => p5);
X--   end block ;
Xend abe111;
*-*-END-of-s-01-1-1-0006a.vhdl-*-*
echo x - s-01-1-2-0002a.vhdl
sed 's/^X//' >s-01-1-2-0002a.vhdl <<'*-*-END-of-s-01-1-2-0002a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X	--
X	--		Copyright Intermetrics 1986
X	--
X	-- 	This material may be reproduced by or for the 
X	--      U.S. Government pursuant to the copyright license 
X	-- 	under DAR clause 7-104.9(a) (1981 May)
X	--
X	--
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-01-1-2-0002A.VHDL
X-- Version: %W% - last modified %E%
X-- sccsid:  -- %G% %W% --
X-- Description:
X-- Check that type, subtype, alias, constant, and attribute
X-- declarations, attribute specifications, subprogram declarations, subprogram
X-- body, signal declarations, file declarations, disconnection specifications
X-- and use statements are allowed  in the entity declarative part.
X-- cjb  7/20/84
X-- JB  (DB 7/10/85)
X-- ADO 05/20/88
X-- 
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xpackage P is
X type BIT is ('0', '1');
Xend P;
X
Xentity E  is
X    port (A:BIT; B:out BIT;
X          C,D : Boolean) ;
X    type Q is range 10.5 to 11.5;
X    subtype R is REAL;
X    alias SA :BIT is A;
X    constant C1 :REAL := 1.39;
X    attribute PIN_NO of A:signal is 10;
X--    assert (not (C and D))
X--         report " Signals to high raise the dam";
X
X--    assert A = '0'  severity warning;
X--    initialize Q to 11.0, 11.1 after 1 ns;
X
Xprocedure P1 is
X begin
X  return;
Xend P1;
X
Xfunction F1 return BIT is
Xbegin
X  return '0';
Xend F1;
X
Xsignal S:BIT;
X-- file declaration not checked at this time
Xdisconnect S:T after 0ns;
Xuse P.all;
Xend E;
X
*-*-END-of-s-01-1-2-0002a.vhdl-*-*
echo x - s-01-1-3-0001a.vhdl
sed 's/^X//' >s-01-1-3-0001a.vhdl <<'*-*-END-of-s-01-1-3-0001a.vhdl-*-*'
X
X----------------------------------------------------------------------
X--
X--
X----------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-01-1-3-0001A.VHDL
X-- Version: %W% - last modified %E%
X-- sccsid:  -- %G% %W% --
X-- Description:
X-- Check that concurrent assertion statements, passive concurrent procedure
X-- calls, and passive process statements are allowed in an entity statement.
X-- ADO 05/20/88
X-- 
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
X port ( A: in BIT;
X        B: out BIT);
X procedure P is
X  begin
X    return;
X end P;
Xbegin
X assert A = '1';
X P;
Xend E;
*-*-END-of-s-01-1-3-0001a.vhdl-*-*
echo x - s-01-2-0-0001a.vhdl
sed 's/^X//' >s-01-2-0-0001a.vhdl <<'*-*-END-of-s-01-2-0-0001a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X	--
X	--		Copyright Intermetrics 1986
X	--
X	-- 	This material may be reproduced by or for the 
X	--      U.S. Government pursuant to the copyright license 
X	-- 	under DAR clause 7-104.9(a) (1981 May)
X	--
X	--
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-01-2-0-0001A.VHDL
X-- Version: %W% - last modified %E%
X-- sccsid:  -- %G% %W% --
X-- Description:
X-- Check that an interface declaration may have one or more bodies associated
X-- with it.
X-- ADO 05/24/88
X-- 
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E1  is
X    port (B:BIT) ;
Xend E1;
X
Xarchitecture B1 of E1 is
X-- BB:block
Xbegin
X  process
X  begin
X    null;
X  end process;
X--  end block;
Xend B1;
X
Xarchitecture B2 of E1 is
X-- BB:block
Xbegin
X  process
X  begin
X    null;
X  end process;
X--  end block;
Xend B2;
X
Xarchitecture B3 of E1 is
X-- BB:block
Xbegin
X  process
X  begin
X    null;
X  end process;
X--  end block;
Xend B3;
X
Xarchitecture B4 of E1 is
X-- BB:block
Xbegin
X  process
X  begin
X    null;
X  end process;
X--  end block;
Xend B4;
X
*-*-END-of-s-01-2-0-0001a.vhdl-*-*
echo x - s-01-2-0-0002a.vhdl
sed 's/^X//' >s-01-2-0-0002a.vhdl <<'*-*-END-of-s-01-2-0-0002a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X	--
X	--		Copyright Intermetrics 1986
X	--
X	-- 	This material may be reproduced by or for the 
X	--      U.S. Government pursuant to the copyright license 
X	-- 	under DAR clause 7-104.9(a) (1981 May)
X	--
X	--
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-01-2-0-0002A.VHDL
X-- Version: %W% - last modified %E%
X-- sccsid:  -- %G% %W% --
X-- Description:
X-- Check that the body name at the end of the body declaration is optional.
X-- ADO 05/24/88
X-- 
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E1  is
X    port (B:BIT) ;
Xend E1;
X
Xarchitecture B1 of E1 is
X-- BB: block
X begin
X  process
X  begin
X    null;
X  end process;
X--end block;
Xend ;
X
Xarchitecture B2 of E1 is
X-- BB: block
X begin
X  process
X  begin
X    null;
X  end process;
X--  end block;
Xend B2;
*-*-END-of-s-01-2-0-0002a.vhdl-*-*
echo x - s-01-2-1-0001a.vhdl
sed 's/^X//' >s-01-2-1-0001a.vhdl <<'*-*-END-of-s-01-2-1-0001a.vhdl-*-*'
X-- /* -*- Mode: vhdl; -*-  */
X-- ************************************************************************
X--  Copyright (C) 1988 Microelectronics and Computer Technology Corporation
X--  - VLSI CAD Program - %Y%
X-- ************************************************************************
X--  File Contents:  Tests For IEEE 1076-1987 VHDL
X--  This file may be redistributed provided the above copyright notice 
X--  appears on all copies and that the further free redistribution of this 
X--  file is not in any way restricted by those who redistribute it.
X--
X--  These VHDL tests are distributed 'as is', without warranties of any kind.
X--
X--  This file is not part of any MCC proprietary or DoD VHDL software.
X-- 
X--     File:       %P%
X--     Author:     Steve Grout
X--     Version:    %W% - last modified %E%
X--     sccsid:     -- %G% %W% --
X--     Description:
X--  contain: subprogram declaration, subprogram body, type declaration,
X--  subtype declaration, constant declaration, signal declaration, file
X--  declaration, alias declaration, component declaration, attribute
X--  declaration, attribute specification, configuration declaration,
X--  disconnection specification, or use clause.
X-- 	
X--     Modification History
X--   --------------------------------------------------------------------
X-- 
X-- **********************************************************************
X-- 
X-- Begin test: >>>
X
Xpackage P is
X type BIT is ('0', '1');
Xend P;
X
Xentity E  is
X    port (A:BIT; B:out BIT;
X          C,D : Boolean) ;
Xend E;
X
Xentity E2 is
X  port (A: in BIT);
Xend E2;
X
Xarchitecture behavior of E2 is
X  begin
X    process
X      begin
X    end process;
Xend E2;
Xarchitecture  A of E is
X
X    procedure P1 is
X      begin
X        return;
X    end P1;
X
X    function F1 return BIT is
X      begin
X        return '0';
X    end F1;
X    
X    type Q is range 10.5 to 11.5;
X    subtype R is REAL;
X    alias SA :BIT is A;
X    constant C1 :REAL := 1.39;
X    signal S :BIT;
X--  file declaration not checked at this time
X--  alias declaration not checked at this time
X    component E1
X        port (A: in BIT);
X    end component;
X    attribute PIN_NO of A:signal is 10;
X    for TEST:E2
X     use entity E2(behavior);
X    disconnect S:T after 0ns;
X    use P.all;
Xbegin
X    TEST: E2 port map (P1);
Xend A;
X
*-*-END-of-s-01-2-1-0001a.vhdl-*-*
echo x - s-01-2-2-0001a.vhdl
sed 's/^X//' >s-01-2-2-0001a.vhdl <<'*-*-END-of-s-01-2-2-0001a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X	--
X	--		Copyright Intermetrics 1986
X	--
X	-- 	This material may be reproduced by or for the 
X	--      U.S. Government pursuant to the copyright license 
X	-- 	under DAR clause 7-104.9(a) (1981 May)
X	--
X	--
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-01-2-2-0001A.VHDL
X-- Version: %W% - last modified %E%
X-- sccsid:  -- %G% %W% --
X-- Description:
X-- Check that concurrent signal assignment, concurrent assertion, generate,
X-- and component instantiation statements are permitted in a set of
X-- statements.  Check that concurrent assertion statements which are
X-- indisguishable from assertion statements and concurrent signal assignment
X-- statements which are indistinguishable from signal assignment statements are
X-- also permitted.
X-- ADO 05-26/88
X-- 
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E  is
X    port ( Pt : in BOOLEAN;
X           PTO : out BIT) ;
Xend E;
X
Xarchitecture AB of E is
X-- L_X_1: block
X  signal S1, S2 : Integer;
X  signal S : INTEGER ;
X
X  component FO port (F1,F2,F3 : INTEGER) ;
Xbegin
X  -- concurrent signal statement
X   S <= transport 5;
X   
X  -- concurrent assertion statement
X   assert ( not PT)
X    report " dead wire "
X    severity WARNING;
X
X  -- generate 
X--   for I in 1 to 5 generate
X--L_X_2:    block
X--     signal S3 : Bit;
X--    begin
X--     S2 <= transport 1;
X--    end block;
X--   end generate;
X
X  -- component instatiation
X    Ls : FO port(S1,S2,S);
X--  end block;
Xend AB;
*-*-END-of-s-01-2-2-0001a.vhdl-*-*
exit


--
Steve Grout @ MCC VLSI CAD Program, Austin TX.  [512] 343-0860 
ARPA: grout@mcc.arpa
UUCP: {ihnp4,seismo,harvard,gatech,pyramid}!ut-sally!im4u!milano!grout