shrenik@pyramis.Eng.Sun.COM (Shrenik Mehta) (08/03/90)
NEW BOOK ANNOUNCEMENT: ---------------------------------------------------------------------------- HARDWARE MODELING WITH VERILOG HDL ---------------------------------- by Eliezer Sternheim Interpretive Systems Rajvir Singh Nexgen Microsystems Yatin Trivedi Sun Microsystems ---------------------------------------------------------------------------- This is the first book about the Verilog Hardware Description Language which has become a standard for designing digital systems and VLSI devices. The book is primarily written for those who have prior knowledge of the Verilog HDL and want to learn more about designing complex devices and large systems. This book is also useful to designers with no Verilog experience but with exposure to other hardware description languages or high level programming languages. A separate chapter is devoted to the introduction of Verilog HDL with emphasis on the behavioral aspects of the language. The book also contains a separate chapter describing some useful tips and techniques in modeling debugging. Two appendices give formal syntax of the language and its reserved keywords. The book contains the following chapters: 1. Why Hardware Description Languages? 2. Anatomy of the Verilog HDL 3. Modeling a Pipelined Processor 4. Modeling System Blocks 5. Modeling Cache Memories 6. Modeling Asynchronous I/O: UART 7. Modeling a Floppy Disk Subsystem 8. Useful Modeling and Debugging Techniques Appendix A: Verilog Formal Syntax Definition Appendix B: Verilog Keywords Each chapter on modeling first describes a piece of hardware, then develops and explains its Verilog model, and at the end, provides a complete listing of the Verilog model. The stress has been to design a piece of hardware at a higher level of abstraction which can be implemented at gate level by some appropriate synthesizer. Check with local bookstores or to order a copy of the book write to the publishers: Automata Publishing Company PO Box 50335 Palo Alto, CA 94303, USA Fax: 415-855-9545 Phone: 408-255-0705 -------------------------------------------------- VOLUME DISCOUNT AVAILABLE FROM PUBLISHER -------------------------------------------------- The souce code for the models can be purchased from the publisher. ************************************************************************** DISCLAIMER: This posting is done as a favor to the authors and I have no personal monetary benefits ************************************************************************** Shrenik Mehta Sun Microsystems shrenik@Eng.Sun.COM
jcallen@Encore.COM (Jerry Callen) (08/03/90)
In article <140081@sun.Eng.Sun.COM> shrenik@pyramis.Eng.Sun.COM (Shrenik Mehta) writes: > [Announcment of new book on Verilog Hardware Description Language] > >This is the first book about the Verilog Hardware Description Language >which has become a standard for designing digital systems and VLSI devices. >The book is primarily written for those who have prior knowledge of the >Verilog HDL and want to learn more about designing complex devices and large >systems. Lemme see now, that's "Verilog Hardware Description Language" - by golly, that's VHDL! I've been hearing all about that lately; something about VHDL use mandated on government work or something. Geez, sounds great! Seems like there is potential for confusing Verilog HDL with: VHSIC Hardware Description Language (VHDL) where VHSIC stands for Very High Speed Integrated Circuit. _This_ VHDL was designed by Intermetrics and is the one the government likes. Of course, for all I know, Verilog HDL may in fact _be_ VHSIC HDL. The language is (I believe) in the public domain, and Intermetrics licenses its VHDL compiler to other companies; I think other companies have also written VHDL compilers. Does anyone KNOW if Verilog HDL is VHSIC HDL? This is not meant as a flame at Verilog (or anyone); I just wanted to head off some possible confusion. -- Jerry Callen jcallen@encore.com Claimer: I used to work at Intermetrics. Several Intermetricians have written a book on VHSIC HDL; I don't recall the title offhand.
gchin@ssf.Eng.Sun.COM (Gary Chin) (08/04/90)
Verilog HDL is not the same as the government standard VHDL, but Verilog HDL is widely used by commercial companies. Gary Chin In article <12363@encore.Encore.COM> jcallen@encore.com (Jerry Callen) writes: >In article <140081@sun.Eng.Sun.COM> shrenik@pyramis.Eng.Sun.COM (Shrenik Mehta) writes: >> [Announcment of new book on Verilog Hardware Description Language] >> >>This is the first book about the Verilog Hardware Description Language >>which has become a standard for designing digital systems and VLSI devices. >>The book is primarily written for those who have prior knowledge of the >>Verilog HDL and want to learn more about designing complex devices and large >>systems. > >Lemme see now, that's "Verilog Hardware Description Language" - by golly, >that's VHDL! I've been hearing all about that lately; something about >VHDL use mandated on government work or something. Geez, sounds great! > >Seems like there is potential for confusing Verilog HDL with: > > VHSIC Hardware Description Language (VHDL) > >where VHSIC stands for Very High Speed Integrated Circuit. _This_ VHDL was >designed by Intermetrics and is the one the government likes. > >Of course, for all I know, Verilog HDL may in fact _be_ VHSIC HDL. The language >is (I believe) in the public domain, and Intermetrics licenses its VHDL >compiler to other companies; I think other companies have also written >VHDL compilers. Does anyone KNOW if Verilog HDL is VHSIC HDL? > >This is not meant as a flame at Verilog (or anyone); I just wanted to >head off some possible confusion. > >-- Jerry Callen > jcallen@encore.com > >Claimer: I used to work at Intermetrics. Several Intermetricians have > written a book on VHSIC HDL; I don't recall the title offhand.
rpw3@rigden.wpd.sgi.com (Rob Warnock) (08/04/90)
In article <12363@encore.Encore.COM> jcallen@encore.com (Jerry Callen) writes: +--------------- | Does anyone KNOW if Verilog HDL is VHSIC HDL? +--------------- No, "Verilog HDL" != VHSIC HDL, but VHSIC == "VHDL". And indeed, Verilog HDL and VHDL are the two main current contenders for hardware behavioral models intended for "compiling" into gates using some form of logic synthesis. From what I can tell with the ASIC vendors I've been talking to, synthesis from Verilog HDL is here "now" (plus or minus a beta test or so), and syn- thesis from VHDL is promised anywhere from "someday" to "real soon" to "as soon as we get the Verilog HDL synthesis software stable". Or to put it another way, "everybody" says VDHL is "the future" and "the way to go" and "required, if you want any government business", but synthesis from a Verilog HDL model is here now. The Verilog simulator itself [the program product from Cadence] is certainly here now, and you can sometimes get even non-ASIC chip vendors to give you [o.k., often under NDA] Verilog behavioral descriptions for their chips, which makes it a lot easier to simulate a board or a system with a mix of standard parts and your custom parts. And wouldn't you know it, those same chip vendors that are so happy to give you the Verilog models for their chips somehow haven't yet gotten around to writing VHDL models for their chips... which is no surprise since most of the big chip vendors use Verilog internally! And of course, synthesis from either Verilog or VHDL functional and gate-level models has been around for a while (though even here Verilog seems to be more common). -Rob p.s. Definition of some terms [to the best of my understanding, may be a little bit "off", I'm still learning this stuff]: "Behavioral model" - a high-level almost black-box description of the relationships between a module's inputs, outputs, and possibly some internal state. In Verilog HDL and in VHDL, one uses "C"-like variables, operators, and flow control primitives. Delays and timing and synchronization may be handled explicitly in the model, or you may choose to do a "zero-delay" model, for more simulation speed. Parallel processes are explicitly supported, as are fork/join, events/wait_for_event, etc. "Functional model" - all you are allowed to do is interconnect instantiations of pre-defined sub-modules from a library, usually provided by a third party CAD software firm. At this level, you might have "counters", "ALUs", "RAMs", "buffers", etc. (When doing board-level functional modelling, these might be chips, e.g. 74F374.) Each library is tuned to a specific ASIC vendor or silicon foundry, and each predefined element accurately reflects the drive, delays, etc., of some "standard cell" (or in the case of gate arrays, pre-defined allocation/interconnection) that achieves that functionality. "Gate-level model" - all you are allowed to do is to specify the interconnects between instantiations of pre-defined low-level "gate" constructs, like AND, OR, NOR, XOR, transmission gate, pull-up, wire (of various capacitances), etc. All higher-level functionality must be expressed in terms of wires and gates. Delays, drive capacity, wire capacitance, etc., are all explicit at this level. "Synthesis" - the automatic transformation or "compiling" of a behavioral or functional model into a gate-level model, possibly with considerable optim- ization. [Gate-level models thus correspond to the "assembly language" of ASIC design, and "assembly" would thus include transforming the gate-level design into the primitive rectangles that make up transistors in silicon, and the placing of the transistors and routing of "wires" (other rectangles of silicon and alum- inum) between them.] ----- Rob Warnock, MS-9U/510 rpw3@sgi.com rpw3@pei.com Silicon Graphics, Inc. (415)335-1673 Protocol Engines, Inc. 2011 N. Shoreline Blvd. Mountain View, CA 94039-7311
davidb@inmet.inmet.com (08/10/90)
/* Written 10:31 am Aug 3, 1990 by jcallen@Encore.COM */ >Seems like there is potential for confusing Verilog HDL with: > VHSIC Hardware Description Language (VHDL) >where VHSIC stands for Very High Speed Integrated Circuit. _This_ VHDL was >designed by Intermetrics and is the one the government likes. Whoa!! Alarm Bells!! Deflector shields up!! Extreme defensive mode on!! The present VHDL (VHSIC Hardware Description Language) is an IEEE standard (1076-1987). To say that it was "designed by Intermetrics" is unfair to a lot of very bright people that worked very hard on the VASG (VHDL Analysis and Standadization Group) during the standardization process. It is true that the language designed for the government by Intermetrics, VHDL 7.2, was used as a baseline by the VASG; however, this language was extensively changed and now must be called a committee effort in every sense of the word (both good and bad). (No flame Jerry --- just setting the record straight). Synthesis from VHDL (or a subset of VHDL) is also "here today" in the form of products by Synopsys, among others. The VHDL text to which Jerry refers is by Lipsett, Shaefer, and Ussary and is published by Kluwar. VHDL is presently in the middle of the re-validation process (required by IEEE rules every five years). It looks as though there will be some fairly extensive changes made during this process. Anyone interested in this process can contact Victor Berman at Cadence in Boston; Victor is head of the North American branch of the VASG. Stan Krowlikowski of IBM in Rochester, MN is chair of the overall VASG. The VHDL User's Group will be meeting at the Claremont resort hotel October 15-17, 1990. For information contact CMS (Conference Management Services) in Menlo Park at (415) 329-0510. It looks like a good group of papers (said the program chair, modestly). The following two days the Design Automation Standards Subcommittee (DASS) will meet. The DASS is the parent group of the VASG. In addition to the VASG other working groups will be meeting. Dave Barton Intermetrics, Inc. barton@i2wash.com