marwan@extro.ucc.su.oz (Marwan Jabri, Sydney Univ. Elec. Eng., Tel: +61-2-692 2240) (11/20/89)
The following VLSI CAD package is available:
PAF
A Package for Algorithmic Floorplanning
PAF offers a variety of graph processing utilities for floorplanning.
For further information on the actual algorithms used in PAF see [1,2,3].
PAF is available on VAX/VMS and Suns. It requires the NAG library.
VMS plotting requires GKS and Suns plotting requires X11r3.
Utilities available within PAF include:
- gracg: Produces a rectangular admissible connectivity graph, that is
performs global routing. Three options are availble for using
passthroughs, wiring blocks and collapsed wiring blocks.
The output is a graph which is rectangularly dualisable.
- cluster: performs clustering on input circuit based on block and
interconnection weights.
- dualise: performs rectangular dualisation, that is, generates rectangular
topology from an input graph.
- minarea: satisfies area constraints (with control over bounding box).
- minshapes: satisfies shape constraints (with control over minimal
block sizes).
- planarise: planarise graph representing input circuit.
- check pin wheels: Checks if a rectangular topology has a pin wheel
structure in it.
- glue: produces a join/join-top instruction for chip assembly.
- plot : plot input graph and output floorplans.
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[1] M.A. Jabri, Automatic building of graphs for rectangular dualisation.
In Proceedings of the ACM/IEEE 25th Design Automation Conference,
Anaheim, pages 638--641, June 1988.
[2] M.A. Jabri and D.J. Skellern, PIAF: A Knowledge-Based/Algorithmic
top-down floorplanning system. In Proceeding of the 26th ACM/IEEE
Design Automation Conference, pages 582--585, Las Vegas,USA, 1989.
[3] M.A. Jabri, A Knowledge-Based/Algorithmic Approach to IC Floorplanning.
PhD thesis, Sydney University Electrical Engineering, 1988.
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PAF is available for Universities at media and handling costs. For
non-Australian universities, the cost is US$150. The cost for Australian
Universities is A$50.00.
For further information, please contact:
Marwan Jabri
Systems Engineering and Design Automation Laboratory
Sydney University Electrical Engineering
NSW 2006 Australia
Tel: +61-2 692 2240
Fax: +61-2 692 3847
Email: marwan@ee.su.oz
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Marwan Jabri E-mail: marwan@ee.su.oz
Systems Engineering and Design Automation Laboratory Fax: (+61-2) 692 3847
Sydney University Electrical Engineering
NSW 2006 Australia