jvb@grad12.cs.duke.edu (Jack V. Briner) (07/02/89)
I am finishing up my Ph.D. work on digital mixed level discrete event
simulation on parallel architectures using optimistic strategies (whew!).
I am looking for very large circuits to simulate (>50,000 transistors or
> 1,000 gates). The simulator (an updated version of Terman's RSIM
running with Mark Horowitz and C.Y. Chu's improved transistor modelling
and with my mixed level additions) takes hilo(tm) like gates and/or sim
files.
If you have a large rnl/rsim circuit you simulate, would you be willing
to send me the sim and al files as well as the vectors/control program
for simulation?
If you have a large HILO simulation, I would also be interested in that too.
One of the problems with determining speedups with various parallel simulators,
is that we don't have a reasonable test-bed. The amount of parallelism that is
extractable from circuits is dependent on the circuit, the machine running
the simulation and the input vectors. I don't want to tune my parallel
simulator too much for the circuits that we have here at Duke.
I would be willing to collect a benchmark set of simulations to distribute
to others who are also trying to do parallel simulation.
Thanks,
Jack
jvb@cs.duke.edu