mark@mips.UUCP (Mark G. Johnson) (09/15/87)
Here are the three public-domain SPICE input circuits that were benchmarked and reported in the companion measurement article. They all run long enough (>250 sec on Vax 11/780) to allow decent measurement precision with the Unix clock. The circuit "decks" are DIGSR: 9-bit digital shift register in 2 micron CMOS BIPOLE: register / clock synchronizer in bipolar TTL TORONTO: Auto-zeroed precision comparator in 3 micron CMOS #--------------------------Cut Here-------------------------- #! /bin/sh # This is a shell archive. Remove anything before the "#! /bin/sh" line, # then unpack it by saving it in a file and typing "sh file." # # unpacks with default permissions # # Contents : digsr bipole toronto # if `test ! -s digsr` then echo "x - digsr" cat > digsr << '@\Rogue\Monster\' * file DIGSR: CMOS digital shift register test case for SPICE * * * .options acct itl1=300 gmin=1e-11 abstol=1e-9 + limpts=205 .width out=133 * * .tran 0.2ns 40ns * ********************************************************************** * * Power supplies * * vd 100 0 dc 5.0 vss 199 0 dc 0.0 * rcc 100 199 1e6 * ********************************************************************** * * Input wiggles (piecewise linear waveforms) * * * vld 210 0 pwl( 0ns 5.0 1ns 5.0 3ns 0v 10ns 0v * vldb 220 0 pwl( 0ns 0v 1ns 0v 3ns 5.0 10ns 5.0 ) * * vck 250 0 pwl( 0ns 5.0 3ns 5.0 6ns 0v 8ns 0v + 11ns 5.0 13ns 5.0 16ns 0v 18ns 0v + 21ns 5.0 23ns 5.0 26ns 0v 28ns 0v + 31ns 5.0 33ns 5.0 36ns 0v 38ns 0v ) * vckb 260 0 pwl( 0ns 0v 3ns 0v 6ns 5.0 8ns 5.0 + 11ns 0v 13ns 0v 16ns 5.0 18ns 5.0 + 21ns 0v 23ns 0v 26ns 5.0 28ns 5.0 + 31ns 0v 33ns 0v 36ns 5.0 38ns 5.0 ) * * vdin 290 0 pwl( 0ns 0v 6ns 0v 8ns 5.0 16ns 5.0 + 18ns 0v 26ns 0v 28ns 5.0 36ns 5.0 + 38ns 0v 40ns 0v ) * * * ra1a 210 0 100K ra2a 220 0 100K ra3a 250 0 100K ra4a 260 0 100K ra5a 290 0 100K * * .ic v(301)=0.00 + v(311)=5.00 + v(321)=0.00 + v(331)=5.00 + v(341)=0.00 + v(351)=0.00 + v(361)=5.00 + v(371)=0.00 + v(381)=5.00 * * ********************************************************************** ********************************************************************** ********************************************************************** * * Circuit Hookup (definition and interconnection) * * * * * * * * * * m900 290 250 301 100 p w=5u l=2u ad=40p pd=20u m901 290 260 301 199 n w=5u l=2u ad=40p pd=20u m902 199 220 301 100 p w=5u l=2u ad=40p pd=20u m903 199 210 301 199 n w=5u l=2u ad=40p pd=20u m904 302 301 100 100 p w=30u l=2u ad=240p pd=45u m905 302 301 199 199 n w=15u l=2u ad=120p pd=30u m906 302 260 303 100 p w=5u l=2u ad=40p pd=20u m907 302 250 303 199 n w=5u l=2u ad=40p pd=20u m908 309 303 100 100 p w=30u l=2u ad=240p pd=45u m909 309 303 199 199 n w=15u l=2u ad=120p pd=30u * * m910 309 250 311 100 p w=5u l=2u ad=40p pd=20u m911 309 260 311 199 n w=5u l=2u ad=40p pd=20u m912 100 220 311 100 p w=5u l=2u ad=40p pd=20u m913 100 210 311 199 n w=5u l=2u ad=40p pd=20u m914 312 311 100 100 p w=30u l=2u ad=240p pd=45u m915 312 311 199 199 n w=15u l=2u ad=120p pd=30u m916 312 260 313 100 p w=5u l=2u ad=40p pd=20u m917 312 250 313 199 n w=5u l=2u ad=40p pd=20u m918 319 313 100 100 p w=30u l=2u ad=240p pd=45u m919 319 313 199 199 n w=15u l=2u ad=120p pd=30u * * m920 319 250 321 100 p w=9u l=2u ad=40p pd=20u m921 319 260 321 199 n w=9u l=2u ad=40p pd=20u m922 199 220 321 100 p w=4u l=2u ad=40p pd=20u m923 199 210 321 199 n w=20u l=2u ad=40p pd=20u m924 322 321 100 100 p w=70u l=2u ad=240p pd=45u m925 322 321 199 199 n w=35u l=2u ad=120p pd=30u m926 322 260 323 100 p w=5u l=2u ad=40p pd=20u m927 322 250 323 199 n w=5u l=2u ad=40p pd=20u m928 329 323 100 100 p w=20u l=2u ad=240p pd=45u m929 329 323 199 199 n w=10u l=2u ad=120p pd=30u * * m930 329 250 331 100 p w=5u l=2u ad=40p pd=20u m931 329 260 331 199 n w=5u l=2u ad=40p pd=20u m932 100 220 331 100 p w=5u l=2u ad=40p pd=20u m933 100 210 331 199 n w=5u l=2u ad=40p pd=20u m934 332 331 100 100 p w=30u l=2u ad=240p pd=45u m935 332 331 199 199 n w=15u l=2u ad=120p pd=30u m936 332 260 333 100 p w=5u l=2u ad=40p pd=20u m937 332 250 333 199 n w=5u l=2u ad=40p pd=20u m938 339 333 100 100 p w=30u l=2u ad=240p pd=45u m939 339 333 199 199 n w=15u l=2u ad=120p pd=30u * * m940 339 250 341 100 p w=5u l=2u ad=40p pd=20u m941 339 260 341 199 n w=5u l=2u ad=40p pd=20u m942 199 220 341 100 p w=5u l=2u ad=40p pd=20u m943 199 210 341 199 n w=5u l=2u ad=40p pd=20u m944 342 341 100 100 p w=30u l=2u ad=240p pd=45u m945 342 341 199 199 n w=15u l=2u ad=120p pd=30u m946 342 260 343 100 p w=5u l=2u ad=40p pd=20u m947 342 250 343 199 n w=5u l=2u ad=40p pd=20u m948 349 343 100 100 p w=30u l=2u ad=240p pd=45u m949 349 343 199 199 n w=15u l=2u ad=120p pd=30u * * m950 349 250 351 100 p w=9u l=2u ad=40p pd=20u m951 349 260 351 199 n w=9u l=2u ad=40p pd=20u m952 199 220 351 100 p w=4u l=2u ad=40p pd=20u m953 199 210 351 199 n w=20u l=2u ad=40p pd=20u m954 352 351 100 100 p w=70u l=2u ad=240p pd=45u m955 352 351 199 199 n w=35u l=2u ad=120p pd=30u m956 352 260 353 100 p w=5u l=2u ad=40p pd=20u m957 352 250 353 199 n w=5u l=2u ad=40p pd=20u m958 359 353 100 100 p w=20u l=2u ad=240p pd=45u m959 359 353 199 199 n w=10u l=2u ad=120p pd=30u * * m960 359 250 361 100 p w=9u l=2u ad=40p pd=20u m961 359 260 361 199 n w=9u l=2u ad=40p pd=20u m962 100 220 361 100 p w=4u l=2u ad=40p pd=20u m963 100 210 361 199 n w=20u l=2u ad=40p pd=20u m964 362 361 100 100 p w=70u l=2u ad=240p pd=45u m965 362 361 199 199 n w=35u l=2u ad=120p pd=30u m966 362 260 363 100 p w=5u l=2u ad=40p pd=20u m967 362 250 363 199 n w=5u l=2u ad=40p pd=20u m968 369 363 100 100 p w=20u l=2u ad=240p pd=45u m969 369 363 199 199 n w=10u l=2u ad=120p pd=30u * * m970 369 250 371 100 p w=5u l=2u ad=40p pd=20u m971 369 260 371 199 n w=5u l=2u ad=40p pd=20u m972 199 220 371 100 p w=5u l=2u ad=40p pd=20u m973 199 210 371 199 n w=5u l=2u ad=40p pd=20u m974 372 371 100 100 p w=30u l=2u ad=240p pd=45u m975 372 371 199 199 n w=15u l=2u ad=120p pd=30u m976 372 260 373 100 p w=5u l=2u ad=40p pd=20u m977 372 250 373 199 n w=5u l=2u ad=40p pd=20u m978 379 373 100 100 p w=30u l=2u ad=240p pd=45u m979 379 373 199 199 n w=15u l=2u ad=120p pd=30u * * m980 379 250 381 100 p w=5u l=2u ad=40p pd=20u m981 379 260 381 199 n w=5u l=2u ad=40p pd=20u m982 100 220 381 100 p w=5u l=2u ad=40p pd=20u m983 100 210 381 199 n w=5u l=2u ad=40p pd=20u m984 382 381 100 100 p w=30u l=2u ad=240p pd=45u m985 382 381 199 199 n w=15u l=2u ad=120p pd=30u m986 382 260 383 100 p w=5u l=2u ad=40p pd=20u m987 382 250 383 199 n w=5u l=2u ad=40p pd=20u m988 389 383 100 100 p w=30u l=2u ad=240p pd=45u m989 389 383 199 199 n w=15u l=2u ad=120p pd=30u * * * * ********************************************************************** * * Outputs (raw output from Spice) * * * * .print tran v(309) v(319) v(339) v(349) + v(359) v(369) v(379) v(389) * * * ********************************************************************** * * MOS model parameters for 2 micron CMOS * .model n nmos + level=2 vto=0.7 tox=400e-10 + nsub=9e15 xj=0.15u ld=0.20u + uo=666 ucrit=.65e5 uexp=0.123 + vmax=5e4 neff=4.0 delta=1.4 + rsh=36 cgso=200p cgdo=200p + cj=200u cjsw=500p mj=0.75 + mjsw=0.30 pb=0.80 nfs=1e11 * * .model p pmos + level=2 vto=-0.70 tox=400e-10 + nsub=7e15 xj=0.06u ld=0.20u + uo=250 ucrit=.85e5 uexp=0.3 + vmax=3e4 neff=2.65 delta=1.0 + rsh=100 cgso=190p cgdo=190p + cj=250u cjsw=350p mj=.55 + mjsw=0.34 pb=0.80 nfs=1e11 * ********************************************************************** * * * * .end @\Rogue\Monster\ else echo "shar: Will not over write digsr" fi if `test ! -s bipole` then echo "x - bipole" cat > bipole << '@\Rogue\Monster\' * file BIPOLE: Schottky TTL edge-triggered register * * .options acct gmin=1e-11 abstol=1e-9 limpts=404 .width out=133 * .tran 0.1ns 18ns * ********************************************************************** * * Power supplies * vcc 100 0 dc 5.0 * rcc 100 0 1e6 * ********************************************************************** * * Input wiggles (piecewise linear waveforms) * vin 170 0 pwl( 0ns 4.0 1ns 4.0 3ns 0.0 10ns 0.0 ) * vinb 171 0 pwl( 0ns 4.0 1ns 4.0 3ns 0.06 10ns 0.0 ) * * ra1a 170 0 100K * * .NODESET V(250)=0.1 + V(260)=0.1 + V(350)=4.0 + V(360)=4.0 + V(450)=0.1 + V(460)=4.0 + V(550)=4.0 + V(560)=0.1 * * ********************************************************************** ********************************************************************** * * Circuit Hookup (definition and interconnection) * * .SUBCKT NAND3 201 202 203 100 400 * * triple emitter transistor R1 100 301 2.8K Q1A 302 301 201 XNPN Q1B 302 301 202 XNPN Q1C 302 301 203 XNPN * * phase splitter R2 100 311 900 Q2 311 302 312 XNPN D2Q 302 311 SD * * squaring network R3 312 313 500 R4 312 314 250 Q3 314 313 0 XNPN D3Q 313 314 SD * * darlington pullup network R5 100 321 40.0 Q4 321 311 322 XNPN D4Q 311 321 SD Q5 321 322 400 XNPN R6 322 0 3.5K * * output pulldown Q6 400 312 0 XNPN D6Q 312 400 SD * * .ENDS NAND3 * * * * * * Inverters to create TTL-driven waveforms * R201 100 201 400.0 XNG1 170 201 201 100 250 NAND3 XNG2 171 201 201 100 260 NAND3 C250 250 0 40P C260 260 0 40P * * * * * Bottom flipflop * R301 100 301 400.0 XNG3 250 460 360 100 350 NAND3 XNG4 260 301 350 100 360 NAND3 C350 350 0 2P C360 360 0 2P * XNG4x 260 301 301 100 367 NAND3 * * * Top flipflop * R401 100 401 400.0 XNG5 360 401 460 100 450 NAND3 XNG6 250 401 450 100 460 NAND3 * XNG6x 450 450 401 100 467 NAND3 * * * * Output flipflop * R501 100 501 400.0 XNG7 460 501 560 100 550 NAND3 XNG8 350 501 550 100 560 NAND3 C550 550 0 40P C560 560 0 40P * * * ********************************************************************** * * Outputs (raw output from Spice) * * * * .print tran v(250) v(260) v(350) v(360) + v(450) v(460) v(550) v(560) * * * * ********************************************************************** * bipolar circuit models * .MODEL SD D( RS=20 CJO=0.1P IS=5E-10 EG=0.69 ) * * .MODEL XNPN NPN( BF=50 BR=1 RB=70 RC=5 CCS=0.8P + TF=0.05E-9 TR=4E-9 IS=1E-14 + CJE=0.4P CJC=0.4P PC=0.85 VA=40 ) * * ********************************************************************** * * * * .end @\Rogue\Monster\ else echo "shar: Will not over write bipole" fi if `test ! -s toronto` then echo "x - toronto" cat > toronto << '@\Rogue\Monster\' * FILE TORONTO: SPICE SIMULATION OF DIFFERENTIAL COMPARATOR * SOURCE: MARK MORAES, UNIVERSITY OF TORONTO {...!decwrl!utcsri!moraes} * * LABELS ************************************** * * VDD = +5.0 volt supply (analog vdd) * Vdgt = +5.0 volt supply (digital vdd) * VSS = 0.0 volt supply (analog gnd) * Vpos = positive input * Vneg = negative input * * vphi1 = PHI1 input clock * vphi2 = PHI2 input clock * vphi3 = PHI3 input clock * * phi1b = #PHI1 input clock (PHI1 bar) * phi2b = #PHI2 input clock (PHI2 bar) * phi3b = #PHI3 input clock (PHI3 bar) * ************************************* * VOLTAGE SOURCES ******************* ************************************* VDD 1 0 DC 5.0V VSS 4 0 DC 0.0V Vdgt 27 0 DC 5.0V * VPOS 13 0 PULSE(-10.0E-5 10.0E-5 0 10NS 10NS 990NS 2000NS) VNEG 19 0 PULSE(10.0E-5 -10.0E-5 0 10NS 10NS 990NS 2000NS) * Vphi1 14 0 PULSE(5.0 0.0 250NS 10NS 10NS 730NS 1000NS) Vphi2 18 0 PULSE(0.0 5.0 260NS 10NS 10NS 710NS 1000NS) Vphi3 26 0 PULSE(0.0 5.0 670NS 10NS 10NS 300NS 1000NS) * Vphi1b 16 0 PULSE(0.0 5.0 250NS 10NS 10NS 730NS 1000NS) Vphi2b 20 0 PULSE(5.0 0.0 260NS 10NS 10NS 710NS 1000NS) Vphi3b 8 0 PULSE(5.0 0.0 670NS 10NS 10NS 300NS 1000NS) * ************************* * LABELS * ************************ * Vout+ = node 24 * Vout- = node 6 * Vpos = node 13 * Vphi1 = node 14 * Vphi2 = node 18 * Vphi3 = node 26 ************************** * HINTS FOR DC CONVERGENCE * (added on 06 May 1987....MGJ) * .NODESET V(5)=1.229 + V(7)=1.229 + V(9)=1.486 + V(10)=1.497 + V(11)=2.823 + V(17)=2.987 + V(21)=3.720 + V(22)=1.486 ************************** * M1 6 5 4 0 NMOS L=3.0U W=21.0U M2 4 5 6 0 NMOS L=3.0U W=21.0U M3 6 5 4 0 NMOS L=3.0U W=21.0U M4 4 5 6 0 NMOS L=3.0U W=21.0U M5 6 8 7 1 PMOS L=3.0U W=13.5U M6 4 10 9 0 NMOS L=3.0U W=18.0U M7 9 12 11 1 PMOS L=3.0U W=24.0U M8 11 12 9 1 PMOS L=3.0U W=36.0U M9 9 12 11 1 PMOS L=3.0U W=36.0U M10 11 12 9 1 PMOS L=3.0U W=36.0U M11 9 12 11 1 PMOS L=3.0U W=36.0U M12 11 12 9 1 PMOS L=3.0U W=36.0U M13 9 12 11 1 PMOS L=3.0U W=36.0U M14 15 14 13 0 NMOS L=3.0U W=6.0U M15 15 16 13 1 PMOS L=3.0U W=13.5U M16 17 9 4 0 NMOS L=3.0U W=4.5U M17 19 18 15 0 NMOS L=3.0U W=6.0U M18 19 20 15 1 PMOS L=3.0U W=13.5U M19 6 16 5 1 PMOS L=3.0U W=13.5U M20 1 17 17 1 PMOS L=3.0U W=6.0U M21 1 21 6 1 PMOS L=3.0U W=21.0U M22 6 21 1 1 PMOS L=3.0U W=21.0U M23 1 21 6 1 PMOS L=3.0U W=21.0U M24 6 21 1 1 PMOS L=3.0U W=21.0U M25 10 17 1 1 PMOS L=6.0U W=6.0U M26 1 21 11 1 PMOS L=3.2U W=119.9U M27 4 22 17 0 NMOS L=3.0U W=4.5U M28 23 18 13 0 NMOS L=3.0U W=6.0U M29 23 20 13 1 PMOS L=3.0U W=13.5U M30 24 16 7 1 PMOS L=3.0U W=13.5U M31 1 21 24 1 PMOS L=3.0U W=21.0U M32 24 21 1 1 PMOS L=3.0U W=21.0U M33 1 21 24 1 PMOS L=3.0U W=21.0U M34 24 21 1 1 PMOS L=3.0U W=21.0U M35 4 10 10 0 NMOS L=3.0U W=4.5U M36 21 4 4 1 PMOS L=58.5U W=6.0U M37 19 14 23 0 NMOS L=3.0U W=6.0U M38 19 16 23 1 PMOS L=3.0U W=13.5U M39 22 10 4 0 NMOS L=3.0U W=18.0U M40 1 21 21 1 PMOS L=3.0U W=6.0U M41 22 25 11 1 PMOS L=3.0U W=24.0U M42 11 25 22 1 PMOS L=3.0U W=36.0U M43 22 25 11 1 PMOS L=3.0U W=36.0U M44 11 25 22 1 PMOS L=3.0U W=36.0U M45 22 25 11 1 PMOS L=3.0U W=36.0U M46 11 25 22 1 PMOS L=3.0U W=36.0U M47 22 25 11 1 PMOS L=3.0U W=36.0U M48 5 8 24 1 PMOS L=3.0U W=13.5U M49 24 7 4 0 NMOS L=3.0U W=21.0U M50 4 7 24 0 NMOS L=3.0U W=21.0U M51 24 7 4 0 NMOS L=3.0U W=21.0U M52 4 7 24 0 NMOS L=3.0U W=21.0U M53 24 26 5 0 NMOS L=3.0U W=6.0U M54 24 14 7 0 NMOS L=3.0U W=6.0U C55 16 25 7.0F M56 22 14 25 0 NMOS L=3.0U W=12.0U C57 7 22 1006.0F C58 23 25 2071.0F C59 16 12 7.0F M60 9 14 12 0 NMOS L=3.0U W=12.0U M61 6 26 7 0 NMOS L=3.0U W=6.0U C62 15 12 2071.0F C63 5 9 1006.0F M64 6 14 5 0 NMOS L=3.0U W=6.0U C65 4 0 674.0F C66 16 0 441.0F C67 14 0 326.0F C68 27 0 1163.0F C69 25 0 605.0F C70 22 0 417.0F C71 23 0 237.0F C72 7 0 285.0F C73 24 0 127.0F C74 26 0 119.0F C75 5 0 293.0F C76 8 0 74.0F C77 11 0 240.0F C78 1 0 412.0F C79 21 0 181.0F C80 18 0 159.0F C81 20 0 58.0F C82 19 0 64.0F C83 10 0 61.0F C84 13 0 63.0F C85 17 0 76.0F C86 6 0 125.0F C87 9 0 418.0F C88 15 0 238.0F C89 12 0 607.0F *************************** * ADD LOAD CAPACITORS * CL1 24 0 1.0P CL2 6 0 1.0P * ************************** * BIAS NETWORK STARTUP RESISTOR * (added on 06 May 1987....MGJ) RCX1 17 10 4E7 * ************************************* * TRANSISTOR MODELS FOR CMOS3 DEVICES **************************************** .MODEL NMOS NMOS( LEVEL=3, TOX=.50E-7, LD=0.26U, UO=785, + PHI=0.73, KAPPA=1, RSH=26, CGSO=3E-10, + CGDO=3E-10, CGBO=2E-10, CJSW=5.6E-10,MJSW=.5, + CJ=8E-4, MJ=.5, VMAX=1E5, + THETA=.110, VTO=0.90, GAMMA=1.15, NSUB=4.0E16) .MODEL PMOS PMOS( LEVEL=3, TOX=.50E-7, LD=0.17U, UO=265, + PHI=0.65, KAPPA=1, RSH=80, CGSO=3E-10, + CGDO=3E-10, CGBO=2E-10, CJSW=3.4E-10,MJSW=.5, + CJ=3.6E-4, MJ=.5, VMAX=6.6E4, + THETA=.135, VTO=-0.74, GAMMA=0.40, NSUB=6E15) .WIDTH OUT=80 .TRAN 10NS 2000NS .OPTIONS ACCT GMIN=1E-11 ABSTOL=1E-9 + LIMPTS=500 .PRINT TRAN V(24,6) V(26) V(13,19) .PRINT TRAN V(24) V(6) V(26) V(13) V(19) .END @\Rogue\Monster\ else echo "shar: Will not over write toronto" fi # to concatenate archives, remove anything after this line exit 0 -- -Mark Johnson *** DISCLAIMER: The opinions above are personal. *** UUCP: {decvax,ucbvax,ihnp4}!decwrl!mips!mark TEL: 408-720-1700 x208 US mail: MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086