mark@mips.com (Mark G. Johnson) (03/04/91)
Paul Vaughan asks about > ... any formula's, algorithms, or tools in common use, >both simple and complex [for estimating area usage on VLSI chips] The following area-estimator formula is often useful, especially for large hunks of design .... in fact it works best for estimating the die area of an entire chip. There's only one parameter ("K") so it's easy to take data from a small number of chips similar to the one you intend to build, and find the "K" that's appropriate for *your* design style: Custom polygon layout? Semicustom using your personally-developed library? Semicustom using a vendor's library? 2 layers of metal? 3 layers? Channel router? River router? Sea-of-gates? etc etc. So get some like-designed chips, measure them, and find the "K" that best predicts the area *of the thing that _you_ are interested in*. This resembles benchmarking, in which customers are advised to use *their own applications* to evaluate hardware. DEFINITION: "Live Transistor area" --- is meant to denote the area (viewed from above like CAD layout systems do) of the actual semiconductor region that forms a transistor. For a MOS transistor, Pchannel or Nchannel, we'll define Live Transistor area == (W x L). For a Bipolar transistor, PNP or NPN, we'll define Live Transistor area == (emitter area). Estimation Formula: Take the sized schematics of a module. Add up all of the Live Transistor areas for each transistor in the module. Multiply by "K". This is the estimate of the layout area of the module. In algebra terms, Area of a module or chip ~=~ K * SUMMATION from i=1 to i=n of (Live_Transistor_area[i]) The value K is a way of quantifying the "transistor density" or transistor efficiency of a design. (1/K) is the percentage of total chip area that's actually occupied by transistors --- the rest is device isolation, latchup-prevention spacings, interconnect, and "waste" (e.g. in a pad- limited die there's lots of blank empty silicon). Here are the K values for two university chips built thru MOSIS: memory chip, hand packed K=16 (6.2% of chip area is custom polygon layout occupied by transistors) microprocessor chip, program K=59 (1.7% of chip area is generated layout, autorouted occupied by transistors) It isn't unthinkable to employ different K's for different kinds of layout; perhaps one K for datapath layout, another for random logic, and maybe a third for embedded RAM, ROM, PLA. This will however increase the amout of work you'll need to do, measuring similar chips to fit several K values. -- -- Mark Johnson MIPS Computer Systems, 930 E. Arques M/S 2-02, Sunnyvale, CA 94086 (408) 524-8308 mark@mips.com {or ...!decwrl!mips!mark}