grout@sunspot.stars.flab.Fujitsu.JUNET (Steve Grout) (07/13/88)
This is Chapter 08 of a 1076-1987 VHDL test suite which was
translated from an 7.2 VHDL version test suite developed by
Intermetrics under funding by the DoD. These tests have been
verified todate mainly against a VHDL 'recognizer' so they may
yet have problems with VHDL semantics. They consist of two
classes of tests,
ERROR Tests: - names which start with 'e' should result in VHDL errors
at the spot where there is a comment about error being expected.
SIMPLE Tests: - names which start with 's' should analyze or compile cleanly.
These tests are being shared back to industry in hopes of getting together
a joint set of tests, checked out and verified, which we can all use to
make sure our various VHDL CAD tools work correctly.
Your comments and especially constructive criticism is urgently requested
via any way we can get it. All replies and resulting changes/updates will
be posted back to the same places these tests were originally posted.
Thanks for your support!
--Steve Grout, MCC CAD Program. (512)338-3516, grout@mcc.com
---- Cut Here and unpack ----
#!/bin/sh
#
# This is a 'shar' archive. Cut out everything above the line
# and unpack them with /bin/sh, i.e., using a command like:
# % sh < {the contents of this message after cutting}
#
#
echo "--------------------------------------------------"
echo "Starting to extract Chapter 08 of a 1076-1987 VHDL"
echo " translated DoD/Intermetrics test suite...."
echo "--------------------------------------------------"
echo x - TEST-SYNOPSIS.text
sed 's/^X//' >TEST-SYNOPSIS.text <<'*-*-END-of-TEST-SYNOPSIS.text-*-*'
X------------------------------------------------------------------------
XChapter: 08-Sequential Tests
X------------------------------------------------------------------------
X
X
X------------------------------------------------------------------------
X Paragraph: 08-Sequential tests
X------------------------------------------------------------------------
XTest: e-08-0-0-0002a.vhdl
X-- Check that an empty statement is not permitted.
XTest: e-08-0-0-0003a.vhdl
X-- Check that concurrent statements are not permitted in a sequence of
X-- statements.
XTest: e-08-0-0-0004a.vhdl
X-- CHECK (as a special case) that generate and component instantiation
X-- statements are not permitted within an if or case statement.
X
XTest: s-08-0-0-0001a.vhdl
X-- Check that all sequential statements are permitted in a sequence of
X-- statements.
XTest: s-08-0-0-0001b.vhdl
X-- Check that an empty sequence of statements is permitted (in process
X-- statements, subprogram declarations, if statements, case statements,
X-- and loop statements).
X
X------------------------------------------------------------------------
X Paragraph: enable stmts --> wait stmts - 8.1.1 --> 8.1
X------------------------------------------------------------------------
XTest: s-08-1-0-0001a.vhdl
X-- Check that each signal name in the signal name list of an WAIT
X-- statement may be any signal including the implicitly
X-- declared signal GUARDS and attributes that are signals.
X
X------------------------------------------------------------------------
X Paragraph: assertion stmts - 8.1.3 --> 8.2
X------------------------------------------------------------------------
XTest: e-08-2-0-0001a.vhdl
X-- Check that the static expression associated with "severity" must be of
X-- type SEVERITY_LEVEL.
XTest: e-08-2-0-0002a.vhdl
X-- Check that the condition in an assertion must be of a boolean type.
XTest: e-08-2-0-0003a.vhdl
X-- Check that the expression associated with "report" must be of type string.
XTest: e-08-2-0-0004a.vhdl
X-- Check that no label is permitted on a sequential assertion statement.
XTest: s-08-2-0-0001a.vhdl
X-- Check that the severity clause is optional.
XTest: s-08-2-0-0002a.vhdl
X-- Check that the report clause is optional.
X
X------------------------------------------------------------------------
X Paragraph: signal assignment stmts - 8.1.4 --> 8.3
X------------------------------------------------------------------------
XTest: e-08-3-0-0001a.vhdl
X-- Check that the name on the left-hand side which is the target of the
X-- assignment cannot be a unit name (of physical literals), the name of a
X-- package, the name of a subprogram, the name of a design entity, a label,
X-- the name of a body declaration, the name of a
X-- type or subtype, or the name of a component.
XTest: e-08-3-0-0002a.vhdl
X-- Check that the left-hand side which is the target of the assignment cannot be
X-- a literal (enumeration, numeric, physical, string).
XTest: e-08-3-0-0003a.vhdl
X-- Check that the left-hand side which is the target of the assignment cannot be
X-- an aggregate.
XTest: e-08-3-0-0004a.vhdl
X-- Check that the left-hand side which is the target of the assignment cannot be
X-- an expression (other than an expression which is a simple name, an indexed
X-- name, a selected name, or a slice name).
XTest: e-08-3-0-0005a.vhdl
X-- Check that the name on the left-hand side which is the target of the
X-- assignment cannot be a variable, an attribute, an input parameter of a function,
X-- a constant, or a generic parameter, or an alias of any of these.
XTest: e-08-3-0-0006a.vhdl
X-- Check that the left-hand side which is the target of the assignment cannot be
X-- a port (or component or subcomponent of a port or an alias of any of these)
X-- whose mode is "in" or "linkage"
XTest: e-08-3-0-0007a.vhdl
X-- Check that all signal names on the left-hand side must be of the same base
X-- type.
XTest: e-08-3-0-0008a.vhdl
X-- Check that when the right-hand side value expression is not of
X-- type universal integer or universal real, the base type of all value
X-- expressions on the right-hand side must be the same as the base type
X-- of the signal(s) on the left-hand side.
XTest: e-08-3-0-0009a.vhdl
X-- Check that a time expression in a waveform element with a static negative
X-- value is not permitted.
XTest: e-08-3-0-0010a.vhdl
X-- Check that multiple time expressions with the same static value in one
X-- waveform are not permitted.
XTest: e-08-3-0-0011a.vhdl
X-- Check that a time expression in a waveform element must be a scalar whose
X-- base type is the the physical type TIME predefined in package STANDARD.
XTest: e-08-3-0-0012a.vhdl
X-- Check that for array signals with static index constraint, even
X-- if the base type are the same the assignment is not permitted
X-- if the number of components are not the same. Check for full
X-- arrays, slices, aggrgates. That is detection of constraint error is by
X-- the analyzer.
XTest: s-08-3-0-0001a.vhdl
X-- Check that there may be multiple signal names (separated by commas) on the
X-- left-hand side (with either a single waveform element or multiple waveform
X-- elements on the right-hand side).
XTest: s-08-3-0-0002a.vhdl
X-- Check that there may be multiple waveform elements (separated by commas) on
X-- the right-hand side (with either a single signal or multiple signals on the
X-- left-hand side).
XTest: s-08-3-0-0003a.vhdl
X-- Check that a time expression may have a static value of zero.
XTest: s-08-3-0-0004a.vhdl
X-- Check that the "after" plus time expression portion of a waveform element is
X-- optional.
XTest: s-08-3-0-0005a.vhdl
X-- Check that the signal name on the left-hand side may be a simple name, an
X-- indexed name, a slice name, a selected name.
XTest: s-08-3-0-0006a.vhdl
X-- Check that implicit type conversion is performed when the right-hand
X-- side value expression is of type universal integer or universal real.
X
X------------------------------------------------------------------------
X Paragraph: updating a projected output waveform - --> 8.3.1
X------------------------------------------------------------------------
X
X------------------------------------------------------------------------
X Paragraph: variable assignment - 8.1.5 --> 8.4
X------------------------------------------------------------------------
XTest: e-08-4-0-0001a.vhdl
X-- Check that the name on the left-hand side which is the target of the
X-- assignment cannot be a unit name (of physical literals), the name of a
X-- package, the name of a subprogram, the name of a design entity, a label,
X-- the name of a body description, the name of a
X-- type or subtype, the name of a component.
XTest: e-08-4-0-0002a.vhdl
X-- Check that the left-hand side which is the target of the assignment cannot be
X-- a literal (enumeration, numeric, physical, string).
XTest: e-08-4-0-0003a.vhdl
X-- Check that the left-hand side which is the target of the assignment cannot be
X-- an aggregate or a slice of an aggregate.
XTest: e-08-4-0-0004a.vhdl
X-- Check that the left-hand side which is the target of the assignment cannot be
X-- an expression (other than an expression which is a simple name, an indexed
X-- name, a selected name, a slice name).
XTest: e-08-4-0-0005a.vhdl
X-- Check that the name on the left-hand side which is the target of the
X-- assignment cannot be a signal, an attribute, an input parameter of a function, a
X-- constant, or a generic parameter, or an alias of any of these.
XTest: e-08-4-0-0006a.vhdl
X-- Check that multiple left-hand side variables are not permitted (analogy to
X-- signal assignment statement).
XTest: e-08-4-0-0007a.vhdl
X-- Check that the subtype of an expression on the right-hand side must be the
X-- same as or convertable to the base type of the object on the left-hand side
X-- to which it is being assigned.
XTest: e-08-4-0-0008a.vhdl
X-- Check that the right-hand side of a variable assignment statement cannot be a
X-- waveform.
XTest: s-08-4-0-0001a.vhdl
X-- Check that the variable name on the left-hand side may be a simple name, an
X-- indexed name, a slice name, a selected name.
XTest: s-08-4-0-0002a.vhdl
X-- Check that implicit type conversion is performed when the right-hand
X-- side value expression is of type universal integer or universal real.
X
X------------------------------------------------------------------------
X Paragraph: array variable assignments - 8.1.5.1 --> 8.4.1
X------------------------------------------------------------------------
XTest: e-08-4-1-1001a.vhdl
X-- Check that for array variables of static index constraints, even if the
X-- base type are the same the assignment is not permitted if the number of
X-- components are not the same. Check for full arrays, slices, aggregates.
X-- That is, detection of constraint error is by analyzer.
X
X------------------------------------------------------------------------
X Paragraph: procedure call stmts - 8.1.6 --> 8.5
X------------------------------------------------------------------------
XTest: e-08-5-0-0001a.vhdl
X-- Check that in a procedure call the type of each argument in the argument
X-- list must be compatible with the type of the corresponding input parameter
X-- in the definition of the procedure. Check for postional inversion of
X-- arguments.
XTest: s-08-5-0-0001a.vhdl
X-- Check that a procedure call without an actual parameter part is permitted
X-- (for procedure with no formal parameters or procedures whose formal
X-- parameters all have default values).
X
X------------------------------------------------------------------------
X Paragraph: if stmts - 8.1.7 --> 8.6
X------------------------------------------------------------------------
XTest: e-08-6-0-0001a.vhdl
X-- Check that an expression specifying a condition in an if statement must be of
X-- a boolean type.
XTest: e-08-6-0-0002a.vhdl
X-- Check that an if statement must end with an "end if".
XTest: e-08-6-0-0003a.vhdl
X-- Check that the else of an enclosing if statement cannot be used to terminate
X-- a nested if statement.
XTest: e-08-6-0-0003b.vhdl
X-- Check that the else of an enclosing if statement cannot be used to terminate
X-- a nested if statement.
XTest: e-08-6-0-0004a.vhdl
X-- Check that else cannot precede elsif in an if statement (check when no elsif
X-- precedes the else).
XTest: e-08-6-0-0005a.vhdl
X-- Check that else cannot precede elsif in an if statement (check when else if
X-- preceded by elsif).
X
X------------------------------------------------------------------------
X Paragraph: case stmts - 8.1.8 --> 8.7
X------------------------------------------------------------------------
XTest: e-08-7-0-0001a.vhdl
X-- Check that the expression in a case statement must be of a discrete type.
X-- Special cases: check that the expression cannot be a string or floating point
X-- type.
XTest: e-08-7-0-0002a.vhdl
X-- Check that each choice in a case statement alternative must be of the same
X-- type as the expression.
XTest: e-08-7-0-0003a.vhdl
X-- Check that if the subtype of the expression is not statically determinable
X-- then each value of the base type of the expression must be represented once
X-- and only once in the set of choices of the case statement. Special case:
X-- Check that a choice defined by a discrete range stands for all values in the
X-- corresponding range. Special case: Check that two choices with overlapping
X-- discrete ranges are not allowed.
XTest: e-08-7-0-0004a.vhdl
X-- Check that if the expression is the name of an object whose subtype is
X-- statically determinable or a qualified expression whose type mark denotes
X-- a static subtype then each value of the subtype must be represented once
X-- and only once in the set of choices of the case statement. Special case:
X-- check for qualified expressions and names of objects of static subtype.
X-- Special case: Check that a choice defined by a discrete range stands
X-- for all values in the corresponding range. Special case: Check that
X-- two choices with overlapping discrete ranges are not allowed.
XTest: e-08-7-0-0005a.vhdl
X-- Check that a simple expression or a discrete range given as a choice in an
X-- alternative must be static.
XTest: e-08-7-0-0006a.vhdl
X-- Check that the choice "others" is allowed only for the last alternative and
X-- as its only choice.
XTest: e-08-7-0-0007a.vhdl
X-- Check that an element simple name is not allowed as a choice of a case
X-- statement alternative.
XTest: e-08-7-0-0008a.vhdl
X-- Check that non-discrete ranges are not allowed in case choices.
X-----------------------------------------------------------------------------
X-- In function P.F and body BB choice types do not match expression type.
X-- In function F and body AB the choice and expression types are non-discrete.
X-----------------------------------------------------------------------------
XTest: e-08-7-0-0009a.vhdl
X-- Check that the lower and upper bounds of a discrete range in case choices
X-- must be the same type.
XTest: e-08-7-0-0010a.vhdl
X-- Check that static violations of range constraints (on case expression) are
X-- detected in lower and upper bounds in range specifications in case choices
X-- (discrete types, discrete types in arrays, discrete types in records).
XTest: e-08-7-0-0011a.vhdl
X-- Check that static violations of the case expression's range constraints are
X-- detected in case choices when choices are not ranges (discrete types,
X-- discrete types in arrays, discrete types in records).
XTest: e-08-7-0-0012a.vhdl
X-- Check static expression evaluation in lower and upper bounds in range
X-- specifications in case choices, all discrete types. Check by violating range
X-- constraint.
XTest: e-08-7-0-0013a.vhdl
X-- Check that even when the context indicates that a case expression covers a
X-- smaller range of values than permitted by its type, an "others" alternative
X-- is required if the type value range is not fully covered by the set of
X-- choices.
XTest: s-08-7-0-0001a.vhdl
X-- Check that the choice "others" may stand for the full set of values of the
X-- expression in a case statement.
XTest: s-08-7-0-0002a.vhdl
X-- Check that the case expression may be a complex static expression.
XTest: s-08-7-0-0003a.vhdl
X-- Check that all discrete types may be used as case expressions. Check for
X-- enumeration (user-defined, predefined( character, bit, boolean))
X-- and integer types.
XTest: s-08-7-0-0004a.vhdl
X-- Check that the choice "others" may stand for a null set of values.
X
X------------------------------------------------------------------------
X Paragraph: loop stmts - 8.1.9 --> 8.8
X------------------------------------------------------------------------
XTest: e-08-8-0-0001a.vhdl
X-- Check that if a label appears at the end of a loop statement, it must
X-- repeat the label at the beginning of the loop statement.
XTest: e-08-8-0-0002a.vhdl
X-- Check that a loop parameter is not allowed on the left-hand side of an
X-- assignment statement.
XTest: e-08-8-0-0003a.vhdl
X-- Check that a condition in an iteration scheme (while) must be of a boolean
X-- type.
XTest: e-08-8-0-0004a.vhdl
X-- Check that a loop parameter is an object whose type is the base type
X-- of the discrete range (check using an equality operation with an
X-- operand of incompatible type).
XTest: e-08-8-0-0005a.vhdl
X-- Check that the discrete range of a loop parameter specification must
X-- have discrete upper and lower bounds.
XTest: e-08-8-0-0006a.vhdl
X-- Check that the scope of the loop parameter is limited to the loop statement
X-- (that is, a reference to it outside the loop statement is illegal).
XTest: e-08-8-0-0007a.vhdl
X-- Check that the upper and lower bounds of the discrete range of a loop
X-- parameter specification must be the same type.
XTest: s-08-8-0-0001a.vhdl
X-- Check that all discrete types may be used as loop parameters. Check for
X-- enumeration (user-defined, predefined( character, bit, boolean) and integer
X-- types.
XTest: s-08-8-0-0002a.vhdl
X-- Check that non-static expressions are permitted as upper and lower bounds
X-- in the discrete range of loop parameter specifications. Special case:
X-- signal or variable names, function invocations, generic parameters.
XTest: s-08-8-0-0003a.vhdl
X-- Check that for static bounds the left boud may be less than, equal to, or
X-- greater than the right bound for either a "to" or "downto" loop parameter
X-- specification discrete range.
XTest: s-08-8-0-0004a.vhdl
X-- Check that the loop label is optional.
X
X------------------------------------------------------------------------
X Paragraph: next stmts - 8.1.1 --> 8.1.a --> 8.9
X------------------------------------------------------------------------
XTest: e-08-9-0-0001a.vhdl
X-- Check that a next statement with a loop label is only allowed within
X-- the labeled loop.
XTest: e-08-9-0-0002a.vhdl
X-- Check that a next statement without a loop label is allowed only within a
X-- labeled or unlabeled loop.
XTest: e-08-9-0-0003a.vhdl
X-- Check that the condition in a next statement must be of a boolean type.
XTest: s-08-9-0-0001a.vhdl
X-- Check that the when clause is optional.
XTest: s-08-9-0-0002a.vhdl
X-- Check that the loop label is optional.
X
X------------------------------------------------------------------------
X Paragraph: exit stmts - 8.1.11 --> 8.1.b --> 8.10
X------------------------------------------------------------------------
XTest: e-08-10-00001a.vhdl
X-- Check that an exit statement with a loop lable is only allowed within the
X-- labeled loop.
XTest: e-08-10-00002a.vhdl
X-- Check that an exit statement without a loop label is allowed only
X-- within the labeled or unlabeled loop.
XTest: e-08-10-00003a.vhdl
X-- Check that the condition in an exit statement must be of a boolean type.
XTest: s-08-10-00001a.vhdl
X-- Check that the when clause is optional.
XTest: s-08-10-00002a.vhdl
X-- Check that the loop label is optional.
X
X------------------------------------------------------------------------
X Paragraph: return stmts - 8.1.12 --> 8.1.c --> 8.11
X------------------------------------------------------------------------
XTest: e-08-11-00001a.vhdl
X-- Check that a return statement can occur only within a subprogram body
X-- or within a process statement (i.e. cannot occur immediately inside a
X-- block statement).
XTest: e-08-11-00002a.vhdl
X-- Check that a return statement in a function must have an associated
X-- expression.
XTest: e-08-11-00003a.vhdl
X-- Check that a return statement in a procedure or process must not have
X-- an associated expression.
XTest: e-08-11-00004a.vhdl
X-- Check that the base type of the expression in the return statement must be
X-- the base type of the type mark that appears in the specification of the
X-- function after the reserved word "return".
XTest: e-08-11-00005a.vhdl
X-- Check that every function body must have at least one return statement.
XTest: e-08-11-00006a.vhdl
X-- Check that in a function when the subtype of the return expression and
X-- the subtype denoted by the type mark occurring after the word "RETURN"
X-- are array of static subtype, both the base type and number of components
X-- must be the same; check for full arrays, slices,aggrgates; that is
X-- detection of constraint error is by the ANALYZER.
XTest: s-08-11-00001a.vhdl
X-- Check that there may be multiple return statements in a function body.
XTest: s-08-11-00002a.vhdl
X-- Check that there may be multiple return statements in a procedure body
X-- or in a process statement.
XTest: s-08-11-00003a.vhdl
X-- Check that there may be a return statement within a compound statement.
XTest: s-08-11-00004a.vhdl
X-- Check that in a function the subtype of the return expression and the
X-- subtype denoted by the type mark occurring after the word "return"
X-- may be different provided both their base types and the number od components
X-- are the same; check for full arrays, slices, aggregates; that is,
X-- detection of constraint error is by th analyzer.
XTest: s-08-11-00005a.vhdl
X-- Check that a return statement is not required in a process statement
X-- or in a procedure body.
X
X------------------------------------------------------------------------
X Paragraph: null stmts - 8.1.13 --> 8.1.d --> 8.12
X------------------------------------------------------------------------
XTest: s-08-12-00001a.vhdl
X-- Check that a null statement is permitted in any sequence of statements.
X-- Check in subprogram bodies and in process, if case, and loop statements.
*-*-END-of-TEST-SYNOPSIS.text-*-*
echo x - e-08-0-0-0002a.vhdl
sed 's/^X//' >e-08-0-0-0002a.vhdl <<'*-*-END-of-e-08-0-0-0002a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-08-1-0-0002A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that an empty statement is not permitted.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
X port (PT: BOOLEAN) ;
Xend E;
X
X
Xarchitecture BB2 of E is
X-- L_X_1: block
X begin
X process
X variable V1: BOOLEAN := TRUE;
X begin
X V1 := V1;
X ;
X -- SYNTAX ERROR: EMPTY STATEMENT NOT ALLOWED
X V1 := V1;
X end process;
X-- end block;
Xend BB2;
X
Xarchitecture AB2 of E is
X-- L_X_2: block
X signal S1: BOOLEAN ;
X begin
X process
X begin
X S1 <= S1;
X ;
X -- SYNTAX ERROR: EMPTY STATEMENT NOT ALLOWED
X S1 <= S1;
X end process;
X-- end block;
Xend AB2;
X
Xuse P.all ;
Xpackage body P is
Xfunction F1 return BOOLEAN is
Xbegin
X ;
X -- SYNTAX ERROR: EMPTY STATEMENT NOT ALLOWED
X return False ;
X end F1;
X
Xfunction F2 return BOOLEAN is
X variable V1: BOOLEAN := TRUE;
Xbegin
X V1 := V1;
X ;
X -- SYNTAX ERROR: EMPTY STATEMENT NOT ALLOWED
X return V1 ;
Xend F2;
Xend P ;
X
Xuse P.all ;
Xpackage body P is
X
X function G1 return BOOLEAN is
X begin
X ;
X -- SYNTAX ERROR: EMPTY STATEMENT NOT ALLOWED
X return False ;
X end G1;
X
X function G2 return BOOLEAN is
X variable V1: BOOLEAN := TRUE;
X begin
X V1 := V1;
X ;
X -- SYNTAX ERROR: EMPTY STATEMENT NOT ALLOWED
X return V1 ;
X end G2;
X
Xend P;
X
Xarchitecture BB2 of E is
X-- L_X_3: block
X signal S1: BOOLEAN ;
X begin
X
X for GP1 in BOOLEAN generate
X ;
X -- SYNTAX ERROR: EMPTY STATEMENT NOT ALLOWED
X end generate;
X
X for GP2 in BOOLEAN generate
X S1 <= S1;
X ;
X -- SYNTAX ERROR: EMPTY STATEMENT NOT ALLOWED
X S1 <= S1;
X end generate;
X process
X variable V1: BOOLEAN := TRUE;
X begin
X
X if FALSE = FALSE then
X ;
X -- SYNTAX ERROR: EMPTY STATEMENT NOT ALLOWED
X end if;
X
X if FALSE = FALSE then
X V1 := V1;
X ;
X -- SYNTAX ERROR: EMPTY STATEMENT NOT ALLOWED
X V1 := V1;
X end if;
X
X if FALSE = FALSE then
X return;
X else
X ;
X -- SYNTAX ERROR: EMPTY STATEMENT NOT ALLOWED
X end if;
X
X if FALSE = FALSE then
X return;
X else
X V1 := V1;
X ;
X -- SYNTAX ERROR: EMPTY STATEMENT NOT ALLOWED
X V1 := V1;
X end if;
X
X for LP in FALSE to TRUE loop
X ;
X -- SYNTAX ERROR: EMPTY STATEMENT NOT ALLOWED
X end loop;
X
X for LP in FALSE to TRUE loop
X V1 := V1;
X ;
X -- SYNTAX ERROR: EMPTY STATEMENT NOT ALLOWED
X V1 := V1;
X end loop;
X
X case TRUE is
X when TRUE =>
X ;
X -- SYNTAX ERROR: EMPTY STATEMENT NOT ALLOWED
X end case;
X
X case TRUE is
X when TRUE =>
X V1 := V1;
X ;
X -- SYNTAX ERROR: EMPTY STATEMENT NOT ALLOWED
X V1 := V1;
X end case;
X
X return;
X end process;
X-- end block;
Xend BB2;
*-*-END-of-e-08-0-0-0002a.vhdl-*-*
echo x - e-08-0-0-0003a.vhdl
sed 's/^X//' >e-08-0-0-0003a.vhdl <<'*-*-END-of-e-08-0-0-0003a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-08-1-0-0003A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that concurrent statements are not permitted in a sequence of
X-- statements.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xuse P.all ;
Xpackage body P is
Xfunction F1 (A:integer) return BOOLEAN is
X constant C : integer := 0;
X variable B : integer := 0;
X variable D : boolean;
Xbegin
X
X B := A;
X if D then
X B := C;
X end if;
X
X if B > C generate -- SYNTAX ERROR: Concurrent statement not permitted
X assert not D; -- in sequence of statements.
X end generate;
X
X return D;
X end F1 ;
Xend P ;
*-*-END-of-e-08-0-0-0003a.vhdl-*-*
echo x - e-08-0-0-0004a.vhdl
sed 's/^X//' >e-08-0-0-0004a.vhdl <<'*-*-END-of-e-08-0-0-0004a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-08-1-0-0004A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- CHECK (as a special case) that generate and component instantiation
X-- statements are not permitted within an if or case statement.
X
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E1 is
X port (A:in BIT; B:in BIT; C:out BIT) ;
Xend E1;
X
Xarchitecture B1 of E1 is
X-- L_X_1: block
X signal S1 : Bit;
X signal S2 : Bit;
X component C1 port (P1 : Bit) ;
X end component ;
Xbegin
X process
X variable V1:INTEGER:=0;
X variable A,B : integer :=0;
X begin
X if (a < b) then
X for I1 in 1 to 5 generate -- ERROR
X S1 <= '0' ;
X end generate;
X null;
X else
X L1 : C1 port map (p1 => S1) ; -- ERROR
X null;
X end IF;
X case a<b is
X when TRUE =>
X for I2 in 1 to 5 generate -- ERROR
X S2 <= '0' ;
X end generate;
X null;
X when FALSE =>
X L2 : C1 port (p1 => S1) ; -- ERROR
X null;
X end case ;
X end process;
X-- end block;
X end B1;
*-*-END-of-e-08-0-0-0004a.vhdl-*-*
echo x - e-08-10-00001a.vhdl
sed 's/^X//' >e-08-10-00001a.vhdl <<'*-*-END-of-e-08-10-00001a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-08-1-B-0001A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that an exit statement with a loop lable is only allowed within the
X-- labeled loop.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
X port (PT:BOOLEAN) ;
Xend E;
X
Xarchitecture BB of E is
X-- L_X_1: block
X begin
X process
X variable V1 : INTEGER;
X begin
X L1: loop
X V1 := 1;
X loop
X V1 := 4;
X end loop;
X end loop L1;
X exit L2; -- ERROR : labelled exit outside named loop
X L2: loop
X V1 := -93;
X end loop L2;
X L3: loop
X V1 := V1 + 3;
X exit L1; -- ERROR : labelled exit inside non-matching loop
X end loop L3;
X return;
X end process;
X-- end block;
Xend BB;
X
Xuse P.all ;
Xpackage P is
X function F return BOOLEAN ;
Xend P ;
X
Xuse P.all ;
Xpackage body P is
Xfunction F return BOOLEAN is
X variable V1 : INTEGER;
Xbegin
X loop
X V1 := 1;
X L1: loop
X V1 := -1;
X end loop L1;
X exit L1; -- ERROR : labelled exit outside matching loop
X end loop;
X return FALSE;
X end F;
Xend P ;
*-*-END-of-e-08-10-00001a.vhdl-*-*
echo x - e-08-10-00002a.vhdl
sed 's/^X//' >e-08-10-00002a.vhdl <<'*-*-END-of-e-08-10-00002a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-08-1-B-0002A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that an exit statement without a loop label is allowed only
X-- within the labeled or unlabeled loop.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
X port (PT:BOOLEAN) ;
Xend E;
X
Xarchitecture BB of E is
X-- L_X_1: block
X begin
X process
X variable V1 : INTEGER;
X begin
X exit; -- ERROR : exit statement outside a loop
X L1: loop
X V1 := 1;
X end loop L1;
X return;
X end process;
X-- end block;
Xend BB;
X
Xuse P.all ;
Xpackage P is
X function F return BOOLEAN ;
Xend P ;
X
Xuse P.all ;
Xpackage body P is
Xfunction F return BOOLEAN is
Xbegin
X exit; -- ERROR : exit statement outside a loop
X return FALSE;
X end F;
Xend P ;
*-*-END-of-e-08-10-00002a.vhdl-*-*
echo x - e-08-10-00003a.vhdl
sed 's/^X//' >e-08-10-00003a.vhdl <<'*-*-END-of-e-08-10-00003a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-08-1-B-0003A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the condition in an exit statement must be of a boolean type.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
X port (PT:BOOLEAN) ;
Xend E;
X
Xarchitecture BB of E is
X-- L_X_1: block
X begin
X process
X variable V1 : INTEGER;
X begin
X L1: loop
X V1 := 1;
X loop
X V1 := 4;
X end loop;
X exit when 'A'; -- ERROR : non-Boolean condition
X end loop L1;
X L2: loop
X V1 := V1 + 3;
X exit when V1 + 3; -- ERROR : non-Boolean condition
X end loop L2;
X return;
X end process;
X-- end block;
Xend BB;
X
Xuse P.all ;
Xpackage P is
X function F return BOOLEAN ;
Xend P ;
X
Xuse P.all ;
Xpackage body P is
Xfunction F return BOOLEAN is
X variable V1 : INTEGER;
Xbegin
X loop
X V1 := 1;
X L1: loop
X V1 := -1;
X exit L1 when V1; -- ERROR : non-Boolean condition
X end loop L1;
X end loop;
X return FALSE;
X end F;
Xend P ;
*-*-END-of-e-08-10-00003a.vhdl-*-*
echo x - e-08-11-00001a.vhdl
sed 's/^X//' >e-08-11-00001a.vhdl <<'*-*-END-of-e-08-11-00001a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-08-1-C-0001A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that a return statement can occur only within a subprogram body
X-- or within a process statement (i.e. cannot occur immediately inside a
X-- block statement).
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
Xend E;
X
Xarchitecture AB of E is
X-- L_X_1: block
X begin
X return; -- ERROR: A RETURN STATEMENT IN A BLOCK ENTITY
X-- end block;
Xend AB;
X
Xarchitecture BB of E is
X-- L_X_2: block
X begin
X for I in 1 to 10 generate
X return; -- ERROR: A RETURN STATEMENT IN A BLOCK ENTITY
X end generate;
X-- end block;
Xend BB;
*-*-END-of-e-08-11-00001a.vhdl-*-*
echo x - e-08-11-00002a.vhdl
sed 's/^X//' >e-08-11-00002a.vhdl <<'*-*-END-of-e-08-11-00002a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-08-1-C-0002A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that a return statement in a function must have an associated
X-- expression.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xpackage P is
X function F return STRING ;
Xend P;
X
Xuse P.all ;
Xpackage body P is
X function F return STRING is
X begin
X return; -- ERROR : function return statement without expression
X end F;
X function G return NATURAL is
X begin
X case '1' and '1' is
X when others => return; -- ERROR : return without expression
X end case;
X return 10;
X end G;
Xend P;
X
Xuse P.all ;
Xpackage P is
X function F return BIT_VECTOR ;
Xend P ;
X
Xuse P.all ;
Xpackage body P is
Xfunction F return BIT_VECTOR is
Xbegin
X return; -- ERROR : function return statement without expression
X end F;
Xend P ;
X
Xuse P.all ;
Xpackage P is
X function G return REAL ;
Xend P ;
X
Xuse P.all ;
Xpackage body P is
Xfunction G return REAL is
Xbegin
X return -9.99;
X if FALSE then
X return; -- ERROR : function return statement without expression
X end if;
X end G;
Xend P ;
*-*-END-of-e-08-11-00002a.vhdl-*-*
echo x - e-08-11-00003a.vhdl
sed 's/^X//' >e-08-11-00003a.vhdl <<'*-*-END-of-e-08-11-00003a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-08-1-C-0003A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that a return statement in a procedure or process must not have
X-- an associated expression.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
X port (PT:BOOLEAN) ;
Xend E;
X
Xarchitecture BB of E is
X-- L_X_1: block
X begin
X process
X begin
X return 23; -- ERROR : return expression in architecture
X end process;
X-- end block;
Xend BB;
X
Xarchitecture BB1 of E is
X-- L_X_2: block
X begin
X process
X begin
X return;
X if 1 /= 10 then
X return 23 - 9; -- ERROR : return expression in architecture
X end if;
X end process;
X-- end block;
Xend BB1;
X
*-*-END-of-e-08-11-00003a.vhdl-*-*
echo x - e-08-11-00004a.vhdl
sed 's/^X//' >e-08-11-00004a.vhdl <<'*-*-END-of-e-08-11-00004a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-08-1-C-0004A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the base type of the expression in the return statement must be
X-- the base type of the type mark that appears in the specification of the
X-- function after the reserved word "return".
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xpackage P is
X function F return STRING ;
X function G return REAL ;
X function H return INTEGER ;
Xend P;
X
Xuse P.all ;
Xpackage body P is
X function F return STRING is
X begin
X return X"F"; -- ERROR : base type does not match return base type
X end F;
X function G return REAL is
X begin
X return F; -- ERROR : base type does not match return base type
X end G;
X function H return INTEGER is
X type I is range -10 to 10;
X variable V : I := -4;
X begin
X return V; -- ERROR : base type does not match return base type
X end H;
Xend P;
X
Xuse P.all ;
Xpackage P is
X function F return TIME ;
Xend P ;
X
Xuse P.all ;
Xpackage body P is
Xfunction F return TIME is
Xbegin
X return "HR"; -- ERROR : base type does not match return base type
X end F;
Xend P ;
X
Xuse P.all ;
Xpackage P is
X function G return BIT_VECTOR ;
Xend P ;
X
Xuse P.all ;
Xpackage body P is
Xfunction G return BIT_VECTOR is
X type AR1 is array (0 to 4) of BIT;
X variable V : AR1;
Xbegin
X V := (others=>BIT ' ('1'));
X return V; -- ERROR : base type does not match return base type
X end G;
Xend P ;
*-*-END-of-e-08-11-00004a.vhdl-*-*
echo x - e-08-11-00005a.vhdl
sed 's/^X//' >e-08-11-00005a.vhdl <<'*-*-END-of-e-08-11-00005a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-08-1-C-0005A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that every function body must have at least one return statement.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xpackage P is
X function F return NATURAL ;
Xend P;
X
Xuse P.all ;
Xpackage body P is
X function F return NATURAL is
X variable V1 : CHARACTER;
X begin
X V1 := 'A';
X V1 := 'B';
X V1 := 'C';
X V1 := 'Z';
X end F; -- ERROR : function body without return statement
Xend P;
X
Xuse P.all ;
Xpackage P is
Xfunction F return BIT ;
Xend P ;
X
Xuse P.all ;
Xpackage body P is
Xfunction F return BIT is
X variable V1 : TIME;
Xbegin
X V1 := 10NS;
X V1 := 3S;
X end F ; -- ERROR : function body without return statement
Xend P ;
X
*-*-END-of-e-08-11-00005a.vhdl-*-*
echo x - e-08-11-00006a.vhdl
sed 's/^X//' >e-08-11-00006a.vhdl <<'*-*-END-of-e-08-11-00006a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-08-1-C-0006A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that in a function when the subtype of the return expression and
X-- the subtype denoted by the type mark occurring after the word "RETURN"
X-- are array of static subtype, both the base type and number of components
X-- must be the same; check for full arrays, slices,aggrgates; that is
X-- detection of constraint error is by the ANALYZER.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xpackage P is
X type IARY is array ( 1 to 1000) of integer range 1 to 10;
X function F1 return IARY ;
X function T1 return IARY ;
X function R1 return IARY ;
X function E1 return IARY ;
X function A2 return IARY ;
X function E2 return IARY ;
Xend p;
X
Xuse P.all ;
Xpackage body P is
X
Xfunction F1 return IARY is
X type RARY is array ( 1 to 1000) of REAL;
X variable RESULT : RARY;
X begin
X return RESULT;
X-- ERROR THE RETURNED VALUE MUST BE THE SAME AS THE TYPE INDICATED AFTER THE
X-- RETURN IN THE FUNCTION DECLARATION
Xend F1 ;
X
Xfunction T1 return IARY is
X type RARY is array ( 1 to 1000) of BOOLEAN;
X variable RESULT : RARY;
X begin
X return RESULT;
X-- ERROR THE RETURNED VALUE MUST BE THE SAME AS THE TYPE INDICATED AFTER THE
X-- RETURN IN THE FUNCTION DECLARATION
Xend T1 ;
X
Xfunction R1 return IARY is
X type RARY is array ( 1 to 100) of INTEGER;
X variable RESULT : RARY;
X begin
X return RESULT;
X-- ERROR THE RETURNED VALUE MUST BE THE SAME AS THE TYPE INDICATED AFTER THE
X-- RETURN IN THE FUNCTION DECLARATION
Xend R1 ;
X
Xfunction E1 return IARY is
X type RARY is array ( 1 to 1000) of INTEGER ;
X
X variable RESULT : RARY;
X begin
X return RESULT;
X-- ERROR THE RETURNED VALUE MUST BE THE SAME AS THE TYPE INDICATED AFTER THE
X-- RETURN IN THE FUNCTION DECLARATION
Xend E1 ;
X
Xfunction A2 return IARY is
Xbegin
X return IARY'(1 to 999 => 5);
X-- ERROR THE RETURNED VALUE MUST BE THE SAME AS THE TYPE INDICATED AFTER THE
X-- RETURN IN THE FUNCTION DECLARATION
Xend A2 ;
X
Xfunction E2 return IARY is
X variable I : IARY;
Xbegin
X return I(1 to 999);
X-- ERROR THE RETURNED VALUE MUST BE THE SAME AS THE TYPE INDICATED AFTER THE
X-- RETURN IN THE FUNCTION DECLARATION
Xend E2;
X
Xend p;
*-*-END-of-e-08-11-00006a.vhdl-*-*
echo x - e-08-2-0-0001a.vhdl
sed 's/^X//' >e-08-2-0-0001a.vhdl <<'*-*-END-of-e-08-2-0-0001a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-08-1-3-0001A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the static expression associated with "severity" must be of
X-- type SEVERITY_LEVEL.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E1 is
X port (B:BIT; C:BIT) ;
Xend E1;
X
Xarchitecture A1 of E1 is
Xbegin
X assert
X B=C
X severity 3.0; --SYNTAX ERROR: assertion severity not of type
X -- SEVERITY_LEVEL
X assert
X B='0'
X severity '1'; --SYNTAX ERROR: assertion severity not of type
X -- SEVERITY_LEVEL
Xend A1 ;
X
*-*-END-of-e-08-2-0-0001a.vhdl-*-*
echo x - e-08-2-0-0002a.vhdl
sed 's/^X//' >e-08-2-0-0002a.vhdl <<'*-*-END-of-e-08-2-0-0002a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-08-1-3-0002A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the condition in an assertion must be of a boolean type.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E1 is
X port (B:BIT; C:BIT) ;
Xend E1;
X
Xarchitecture A1 of E1 is
Xbegin
X assert
X B; --SEMANTICS ERROR: assertion expression not boolean
Xend A1;
Xarchitecture A2 of E1 is
Xbegin
X
Xend A2 ;
X
*-*-END-of-e-08-2-0-0002a.vhdl-*-*
echo x - e-08-2-0-0003a.vhdl
sed 's/^X//' >e-08-2-0-0003a.vhdl <<'*-*-END-of-e-08-2-0-0003a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-08-1-3-0003A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the expression associated with "report" must be of type string.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E1 is
X port (B:BIT; C:BIT) ;
Xend E1;
X
X
Xarchitecture A1 of E1 is
X
Xbegin
X assert
X B=C
X report 1 --SEMANTICS ERROR: assertion report is not a string lit.
X severity ERROR;
Xend A1 ;
X
X
X
*-*-END-of-e-08-2-0-0003a.vhdl-*-*
echo x - e-08-2-0-0004a.vhdl
sed 's/^X//' >e-08-2-0-0004a.vhdl <<'*-*-END-of-e-08-2-0-0004a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-08-1-3-0004A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that no label is permitted on a sequential assertion statement.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E1 is
X port (B1: BIT; C1 : BIT) ;
Xend E1;
X
Xarchitecture A1 of E1 is
X
X-- BL: block
X begin
X process
X begin
X erlab: assert
X -- ERROR: no label is permitted on a sequential assertion statement
X B1 = C1
X severity ERROR;
X end process;
X-- end block;
Xend A1;
*-*-END-of-e-08-2-0-0004a.vhdl-*-*
echo x - e-08-3-0-0001a.vhdl
sed 's/^X//' >e-08-3-0-0001a.vhdl <<'*-*-END-of-e-08-3-0-0001a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-08-1-4-0001A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the name on the left-hand side which is the target of the
X-- assignment cannot be a unit name (of physical literals), the name of a
X-- package, the name of a subprogram, the name of a design entity, a label,
X-- the name of a body declaration, the name of a
X-- type or subtype, or the name of a component.
X-- JB (DB 7/17/85)
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xuse PACK_1.all ;
Xpackage body PACK_1 is
X function FUN_1 return TIME is
X begin
X return 1 min;
X end FUN_1;
X procedure PROC_1 is
X begin
X null;
X end PROC_1;
Xend PACK_1;
X
X-- with package PACK_1;
Xuse PACK_1.all;
Xentity ENT_1 is
X port (X,Y: in BIT; COUT: out BIT) ;
Xend ENT_1;
X
Xarchitecture BB_1 of ENT_1 is
X-- B: block
X begin
X process
X variable VAR_1:BIT := '1';
X variable INIT_1: INTEGER := 1;
X begin
X hr <= VAR_1;
X --ERROR: A UNIT NAME (OF A PHYSICAL LITERAL) CANNOT BE THE NAME USED ON
X -- THE LEFT-HAND SIDE OF A SIGNAL ASSIGNMENT
X LOOP_1:
X for i in 1 to 1 loop
X INIT_1 := INIT_1 + 1;
X end loop LOOP_1;
X LOOP_1 <= VAR_1;
X --ERROR: A LOOP LABEL CANNOT BE THE NAME USED ON
X -- THE LEFT-HAND SIDE OF A SIGNAL ASSIGNMENT
X B <= VAR_1;
X --ERROR: A BLOCK LABEL CANNOT BE THE NAME USED ON
X -- THE LEFT-HAND SIDE OF A SIGNAL ASSIGNMENT
X end process;
X-- end block B;
Xend BB_1;
X
Xarchitecture AB_1 of ENT_1 is
X-- L_X_1: block
X component COMP_1 port (A: in BIT; D : out BIT);
X end component ;
X type INIT_1 is range 1 to 1000;
X subtype SUBI_1 is INIT_1 range 10 to 20;
X signal S1 : BIT;
X begin
X GEN_1:
X for i in 1 to 1 generate
X C1: COMP_1 port map (X, COUT);
X end generate GEN_1;
X P: process
X begin
X PACK_1 <= S1;
X --ERROR: A PACKAGE NAME CANNOT BE THE NAME USED ON
X -- THE LEFT-HAND SIDE OF A SIGNAL ASSIGNMENT
X FUN_1 <= S1;
X --ERROR: A FUNCTION NAME CANNOT BE THE NAME USED ON
X -- THE LEFT-HAND SIDE OF A SIGNAL ASSIGNMENT
X PROC_1 <= S1;
X --ERROR: A PROCEDURE NAME CANNOT BE THE NAME USED ON
X -- THE LEFT-HAND SIDE OF A SIGNAL ASSIGNMENT
X ENT_1 <= S1;
X --ERROR: A DESIGN ENTITY NAME CANNOT BE THE NAME USED ON
X -- THE LEFT-HAND SIDE OF A SIGNAL ASSIGNMENT
X GEN_1 <= S1;
X --ERROR: A GENERATE LABEL CANNOT BE THE NAME USED ON
X -- THE LEFT-HAND SIDE OF A SIGNAL ASSIGNMENT
X BB_1 <= S1;
X --ERROR: A BODY DECLARATION NAME CANNOT BE THE NAME USED ON
X -- THE LEFT-HAND SIDE OF A SIGNAL ASSIGNMENT
X INIT_1 <= S1;
X --ERROR: A TYPE NAME CANNOT BE THE NAME USED ON
X -- THE LEFT-HAND SIDE OF A SIGNAL ASSIGNMENT
X SUBI_1 <= S1;
X --ERROR: A SUBTYPE NAME CANNOT BE THE NAME USED ON
X -- THE LEFT-HAND SIDE OF A SIGNAL ASSIGNMENT
X COMP_1 <= S1;
X --ERROR: A COMPONENT NAME CANNOT BE THE NAME USED ON
X -- THE LEFT-HAND SIDE OF A SIGNAL ASSIGNMENT
X C1 <= S1;
X --ERROR: A COMPONENT LABEL CANNOT BE THE NAME USED ON
X -- THE LEFT-HAND SIDE OF A SIGNAL ASSIGNMENT
X P <= S1;
X --ERROR: A PROCESS LABEL CANNOT BE THE NAME USED ON
X -- THE LEFT-HAND SIDE OF A SIGNAL ASSIGNMENT
X end process;
X-- end block;
Xend AB_1;
*-*-END-of-e-08-3-0-0001a.vhdl-*-*
echo x - e-08-3-0-0002a.vhdl
sed 's/^X//' >e-08-3-0-0002a.vhdl <<'*-*-END-of-e-08-3-0-0002a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-08-1-4-0002A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the left-hand side which is the target of the assignment cannot be
X-- a literal (enumeration, numeric, physical, string).
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity ENT_1 is
X port (X,Y: in BIT; COUT: out BIT) ;
Xend ENT_1;
X
Xarchitecture AB_1 of ENT_1 is
X-- L_X_1: block
X
X type R is (LOW, MIDDLE, TOP);
X signal S1:BIT ;
X begin
X process
X begin
X LOW <= S1;
X --ERROR: AN ENUMERATION LITERAL CANNOT BE THE NAME USED ON THE LEFT-HAND
X -- SIDE OF A SIGNAL ASSIGNMENT
X
X '0' <= S1;
X --ERROR: AN ENUMERATION LITERAL CANNOT BE THE NAME USED ON THE LEFT-HAND
X -- SIDE OF A SIGNAL ASSIGNMENT
X
X min <= S1;
X --ERROR: A PHYSICAL LITERAL CANNOT BE THE NAME USED ON THE LEFT-HAND
X -- SIDE OF A SIGNAL ASSIGNMENT
X
X 60 min <= S1;
X --ERROR: A NUMERIC LITERAL CANNOT BE THE NAME USED ON THE LEFT-HAND
X -- SIDE OF A SIGNAL ASSIGNMENT
X
X 0.0 <= S1;
X --ERROR: A NUMERIC LITERAL CANNOT BE THE NAME USED ON THE LEFT-HAND
X -- SIDE OF A SIGNAL ASSIGNMENT
X
X 2#111# <= S1;
X --ERROR: A NUMERIC LITERAL CANNOT BE THE NAME USED ON THE LEFT-HAND
X -- SIDE OF A SIGNAL ASSIGNMENT
X
X "LITERAL" <= S1;
X --ERROR: A STRING LITERAL CANNOT BE THE NAME USED ON THE LEFT-HAND
X -- SIDE OF A SIGNAL ASSIGNMENT
X end process;
X-- end block;
Xend AB_1;
*-*-END-of-e-08-3-0-0002a.vhdl-*-*
echo x - e-08-3-0-0003a.vhdl
sed 's/^X//' >e-08-3-0-0003a.vhdl <<'*-*-END-of-e-08-3-0-0003a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-08-1-4-0003A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the left-hand side which is the target of the assignment cannot be
X-- an aggregate.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity ENT_1 is
X port (X,Y: in BIT; COUT: out BIT) ;
Xend ENT_1;
X
Xarchitecture AB_1 of ENT_1 is
X-- L_X_1: block
X
X type AR_1 is array (INTEGER range <>) of BOOLEAN;
X subtype ARAY is AR_1 (1 to 10);
X type REC_1 is record
X RE_1 : INTEGER;
X RE_2 : BOOLEAN;
X end record;
X signal S1:BIT ;
X signal S2: ARAY ;
X signal S3: REC_1;
X signal S4: ARAY;
X signal S5: REC_1;
X begin
X process
X begin
X (RE_1 => 2) <= 2 after 2 ns;
X --ERROR: AGGREGATES CANNOT BE A TARGET ON THE LEFT-HAND SIDE OF
X -- A SIGNAL ASSIGNMENT
X
X (1, 5, 9, 2) <= 2 after 2 ns;
X --ERROR: AGGREGATES CANNOT BE A TARGET ON THE LEFT-HAND SIDE OF
X -- A SIGNAL ASSIGNMENT
X
X (others => FALSE) <= 2 after 2 ns;
X --ERROR: AGGREGATES CANNOT BE A TARGET ON THE LEFT-HAND SIDE OF
X -- A SIGNAL ASSIGNMENT
X end process;
X-- end block;
Xend AB_1;
*-*-END-of-e-08-3-0-0003a.vhdl-*-*
echo x - e-08-3-0-0004a.vhdl
sed 's/^X//' >e-08-3-0-0004a.vhdl <<'*-*-END-of-e-08-3-0-0004a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-08-1-4-0004A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the left-hand side which is the target of the assignment cannot be
X-- an expression (other than an expression which is a simple name, an indexed
X-- name, a selected name, or a slice name).
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xuse PACK_1.all ;
Xpackage body PACK_1 is
X function FUN_1 return BOOLEAN is
X begin
X return FALSE;
X end FUN_1;
Xend PACK_1;
X
X-- with package PACK_1;
Xuse PACK_1.all ;
Xentity ENT_1 is
X port (X,Y: in BIT; COUT: out BIT) ;
Xend ENT_1;
X
Xarchitecture AB_1 of ENT_1 is
X-- BB : block
X type ENUM_1 is (ONE,TWO,THREE);
X type ENUM_2 is (ONE,THREE,FIVE);
X type INIT_1 is range 16#1# to 16#FF#;
X signal S1,S2,S3: BIT;
X signal S4: ENUM_1 ;
X signal S5: INTEGER;
X begin
X process
X begin
X S1 > S2 <= S3;
X --ERROR: RELATIONAL EXPRESSIONS ARE NOT ALLOWED ON THE LEFT-HAND
X -- SIDE OF A SIGNAL ASSIGNMENT
X
X S2 and S3 <= S1;
X --ERROR: LOGICAL EXPRESSIONS ARE NOT ALLOWED ON THE LEFT-HAND
X -- SIDE OF A SIGNAL ASSIGNMENT
X
X S5**2 <= S5;
X --ERROR: SIMPLE EXPRESSIONS ARE NOT ALLOWED ON THE LEFT-HAND
X -- SIDE OF A SIGNAL ASSIGNMENT
X
X abs S5 <= S5;
X --ERROR: SIMPLE EXPRESSIONS ARE NOT ALLOWED ON THE LEFT-HAND
X -- SIDE OF A SIGNAL ASSIGNMENT
X
X 5.2E1 <= S5;
X --ERROR: LITERAL EXPRESSIONS ARE NOT ALLOWED ON THE LEFT-HAND
X -- SIDE OF A SIGNAL ASSIGNMENT
X
X TWO - ONE <= S4;
X --ERROR: LITERAL EXPRESSIONS ARE NOT ALLOWED ON THE LEFT-HAND
X -- SIDE OF A SIGNAL ASSIGNMENT
X
X FUN_1 <= S1;
X --ERROR: FUNCTION CALLS ARE NOT ALLOWED ON THE LEFT-HAND
X -- SIDE OF A SIGNAL ASSIGNMENT
X
X INIT_1(S5) <= S5;
X --ERROR: TYPE CONVERSIONS ARE NOT ALLOWED ON THE LEFT-HAND
X -- SIDE OF A SIGNAL ASSIGNMENT
X
X ENUM_1'(S4) <= S4;
X --ERROR: QUALIFIED EXPRESSIONS ARE NOT ALLOWED ON THE LEFT-HAND
X -- SIDE OF A SIGNAL ASSIGNMENT
X
X end process;
X-- end block BB ;
Xend AB_1;
X
*-*-END-of-e-08-3-0-0004a.vhdl-*-*
echo x - e-08-3-0-0005a.vhdl
sed 's/^X//' >e-08-3-0-0005a.vhdl <<'*-*-END-of-e-08-3-0-0005a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-08-1-4-0005A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the name on the left-hand side which is the target of the
X-- assignment cannot be a variable, an attribute, an input parameter of a function,
X-- a constant, or a generic parameter, or an alias of any of these.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xuse PACK_1.all ;
Xpackage body PACK_1 is
X type AR_1 is array (1 to 10) of BIT;
X function FUN_1 (PAR_1:BIT) return BIT is
X variable RESULT : bit ;
X begin
X RESULT := '1';
X return RESULT;
X end FUN_1;
X
X function FUN_2 (PAR_2:BIT := '1') return BIT is
X variable VAR_1: BIT := '0';
X variable RESULT : bit ;
X begin
X PAR_2 <= VAR_1;
X --ERROR: AN INPUT PARAMETER OF A FUNCTION CANNOT BE THE NAME USED ON THE
X -- LEFT-HAND SIDE OF A SIGNAL ASSIGNMENT
X RESULT := '1';
X return RESULT;
X end FUN_2;
Xend PACK_1;
X
Xentity ENT_1 is
X generic (PARM_A: TIME := 3 ns) ;
X port (X,Y: in BIT; COUT: out BIT) ;
X alias ALIAN_E1: TIME is PARM_A;
Xend ENT_1;
X
Xarchitecture BB_1 of ENT_1 is
X-- L_X_1: block
X component COMP_1
X generic (P_1 : TIME) ;
X port (A: in BIT; SOUT: out BIT) ;
X end component ;
X type AR_1 is array (1 to 10) of BIT;
X signal S1:BIT ;
X signal S2: AR_1;
X begin
X process
X variable VAR_1: INTEGER;
X variable VAR_2: BIT := '0';
X constant VAR_3: INTEGER := 3;
X
Xbegin
X VAR_1 <= VAR_2;
X --ERROR: A VARIABLE CANNOT BE THE NAME USED ON THE LEFT-HAND
X -- SIDE OF A SIGNAL ASSIGNMENT
X
X AR_1'LOW <= S1;
X --ERROR: AN ATTRIBUTE CANNOT BE THE NAME USED ON THE LEFT-HAND
X -- SIDE OF A SIGNAL ASSIGNMENT
X
X PARM_A <= S1;
X --ERROR: A GENERIC PARAMETER CANNOT BE THE NAME USED ON THE LEFT-HAND
X -- SIDE OF A SIGNAL ASSIGNMENT
X
X end process;
X-- end block;
Xend BB_1;
X
X
*-*-END-of-e-08-3-0-0005a.vhdl-*-*
echo x - e-08-3-0-0006a.vhdl
sed 's/^X//' >e-08-3-0-0006a.vhdl <<'*-*-END-of-e-08-3-0-0006a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-08-1-4-0006A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the left-hand side which is the target of the assignment cannot be
X-- a port (or component or subcomponent of a port or an alias of any of these)
X-- whose mode is "in" or "linkage"
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity ENT_1 is
X port (X,Y: in BIT_VECTOR; Z:linkage BIT_VECTOR; COUT: out BIT);
X alias ALIAN_1: BIT_VECTOR (1 to 10) is X (1 to 10);
X alias ALIAN_2: BIT_VECTOR (1 to 10) is Z(1 to 10);
Xend ENT_1;
X
Xarchitecture AB_1 of ENT_1 is
X-- L_X_1: block
X
X component COMP_1
X generic (P_1 : TIME) ;
X port (A: in BIT; B: linkage BIT; SOUT: out BIT) ;
X end component ;
X signal S1:BIT ;
X begin
X process
X begin
X X <= S1;
X --ERROR: A PORT WHOSE MODE IS "IN" OR "LINKAGE" CANNOT BE
X -- ON THE LEFT-HAND SIDE OF A SIGNAL ASSIGNMENT
X
X Z <= S1;
X --ERROR: A PORT WHOSE MODE IS "IN" OR "LINKAGE" CANNOT BE
X -- ON THE LEFT-HAND SIDE OF A SIGNAL ASSIGNMENT
X
X ALIAN_1 <= S1;
X --ERROR: AN ALIAS FOR A PORT WHOSE MODE IS "IN" OR "LINKAGE" CANNOT BE
X -- ON THE LEFT-HAND SIDE OF A SIGNAL ASSIGNMENT
X
X ALIAN_2 <= S1;
X --ERROR: AN ALIAS FOR A PORT WHOSE MODE IS "IN" OR "LINKAGE" CANNOT BE
X -- ON THE LEFT-HAND SIDE OF A SIGNAL ASSIGNMENT
X
X X(2) <= S1 after 2ns;
X --ERROR: AN ALIAS FOR A PORT WHOSE MODE IS "IN" OR "LINKAGE" CANNOT BE
X -- ON THE LEFT-HAND SIDE OF A SIGNAL ASSIGNMENT
X
X Y(10) <= S1, '1' after 10 ns;
X --ERROR: AN ALIAS FOR A PORT WHOSE MODE IS "IN" OR "LINKAGE" CANNOT BE
X -- ON THE LEFT-HAND SIDE OF A SIGNAL ASSIGNMENT
X
X ALIAN_1(2) <= S1;
X --ERROR: AN ALIAS FOR A PORT WHOSE MODE IS "IN" OR "LINKAGE" CANNOT BE
X -- ON THE LEFT-HAND SIDE OF A SIGNAL ASSIGNMENT
X
X ALIAN_2(10) <= S1, '1' after 10 ns;
X --ERROR: AN ALIAS FOR A PORT WHOSE MODE IS "IN" OR "LINKAGE" CANNOT BE
X -- ON THE LEFT-HAND SIDE OF A SIGNAL ASSIGNMENT
X end process;
X-- end block;
Xend AB_1;
*-*-END-of-e-08-3-0-0006a.vhdl-*-*
echo x - e-08-3-0-0007a.vhdl
sed 's/^X//' >e-08-3-0-0007a.vhdl <<'*-*-END-of-e-08-3-0-0007a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-08-1-4-0007A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that all signal names on the left-hand side must be of the same base
X-- type.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
X
Xentity ENT_1 is
X port (X,Y: in BIT; S: out TIME; COUT: out BIT) ;
Xend ENT_1;
X
Xarchitecture BB_1 of ENT_1 is
X-- L_X_1: block
X signal S1:BIT;
X signal S2: NATURAL;
X signal S3: TIME;
X begin
X process
X variable VAR_1: TIME;
X begin
X ( S, COUT ) <= VAR_1;
X --ERROR: ALL SIGNAL NAMES ON THE LEFT-HAND SIDE MUST BE OF THE SAME BASE TYP
X ( S,S3,S1 ) <= X;
X --ERROR: ALL SIGNAL NAMES ON THE LEFT-HAND SIDE MUST BE OF THE SAME BASE TYP
X ( S1,S2,S3 ) <= '1' after 2 ns;
X --ERROR: ALL SIGNAL NAMES ON THE LEFT-HAND SIDE MUST BE OF THE SAME BASE TYP
X return;
X end process;
X-- end block;
Xend BB_1;
*-*-END-of-e-08-3-0-0007a.vhdl-*-*
echo x - e-08-3-0-0008a.vhdl
sed 's/^X//' >e-08-3-0-0008a.vhdl <<'*-*-END-of-e-08-3-0-0008a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-08-1-4-0008A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that when the right-hand side value expression is not of
X-- type universal integer or universal real, the base type of all value
X-- expressions on the right-hand side must be the same as the base type
X-- of the signal(s) on the left-hand side.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
X
Xentity ENT_1 is
X port (X,Y: in BIT; S: out TIME; COUT: out BIT) ;
Xend ENT_1;
X
Xarchitecture BB_1 of ENT_1 is
X-- L_X_1: block
X
X component COMP_1
X generic (P_1 : TIME) ;
X port (A: in BIT; SOUT: out BIT) ;
X end component ;
X type INIT_1 is range 1 to 300;
X type ENUM_2 is (ONE,TWO,THREE);
X type AR_2 is array (INTEGER range <>) of BOOLEAN;
X signal S1: BIT ;
X signal S2: ENUM_2 ;
X signal S3: AR_2 (1 to 10);
X signal S4: INIT_1 ;
X begin
X process
X type ENUM_1 is (ONE,TWO,THREE);
X type AR_1 is array (INTEGER range <>) of BOOLEAN;
X variable VAR_1: ENUM_1 := ONE;
X variable VAR_2: INTEGER;
X begin
X COUT <= VAR_2;
X --ERROR: THE BASE TYPE OF ALL EXPRESSIONS ON THE RIGHT-HAND SIDE MUST BE
X -- THE SAME AS THE BASE TYPE OF THE SIGNAL ON THE LEFT-HAND SIDE.
X S <= VAR_1 after 2 ns, '1' after 4 ns;
X --ERROR: THE BASE TYPE OF ALL EXPRESSIONS ON THE RIGHT-HAND SIDE MUST BE
X -- THE SAME AS THE BASE TYPE OF THE SIGNAL ON THE LEFT-HAND SIDE.
X S1 <= S3 after 2 ns, S2 after 4 ns;
X --ERROR: THE BASE TYPE OF ALL EXPRESSIONS ON THE RIGHT-HAND SIDE MUST BE
X -- THE SAME AS THE BASE TYPE OF THE SIGNAL ON THE LEFT-HAND SIDE.
X COUT <= S4;
X --ERROR: THE BASE TYPE OF ALL EXPRESSIONS ON THE RIGHT-HAND SIDE MUST BE
X -- THE SAME AS THE BASE TYPE OF THE SIGNAL ON THE LEFT-HAND SIDE.
X end process;
X-- end block;
Xend BB_1;
*-*-END-of-e-08-3-0-0008a.vhdl-*-*
echo x - e-08-3-0-0009a.vhdl
sed 's/^X//' >e-08-3-0-0009a.vhdl <<'*-*-END-of-e-08-3-0-0009a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-08-1-4-0009A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that a time expression in a waveform element with a static negative
X-- value is not permitted.
X-- JB (DB 9/5/85)
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity ENT_1 is
X port (X,Y: in BIT; COUT: out BIT) ;
Xend ENT_1;
X
Xarchitecture AB_1 of ENT_1 is
X-- L_X_1: block
X component COMP_1
X generic (P_1 : TIME);
X port (A: in BIT; SOUT: out BIT) ;
X end component ;
X signal S1:BIT ;
X signal S2: NATURAL;
X begin
X process
X constant NEG: TIME := -2 ns; -- ERROR
X begin
X S1 <= '1' after -5 ns;
X --ERROR: TIME EXPRESSIONS IN A WAVEFORM ELEMENT WITH A STATIC NEGATIVE
X -- VALUE IS NOT PERMITTED
X S2 <= 15 after NEG;
X --ERROR: TIME EXPRESSIONS IN A WAVEFORM ELEMENT WITH A STATIC NEGATIVE
X -- VALUE IS NOT PERMITTED
X end process;
X-- end block;
Xend AB_1;
*-*-END-of-e-08-3-0-0009a.vhdl-*-*
echo x - e-08-3-0-0010a.vhdl
sed 's/^X//' >e-08-3-0-0010a.vhdl <<'*-*-END-of-e-08-3-0-0010a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-08-1-4-0010A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that multiple time expressions with the same static value in one
X-- waveform are not permitted.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
X
Xentity ENT_1 is
X port (X,Y: in BIT; COUT: out BIT) ;
Xend ENT_1;
X
Xarchitecture AB_1 of ENT_1 is
X-- L_X_1: block
X component COMP_1
X generic (P_1 : TIME);
X port (A: in BIT; SOUT: out BIT);
X end component ;
X signal S1:BIT ;
X begin
X process
X constant S2: TIME := 2 ns;
X begin
X COUT <= S1 after 5 ns, '1' after 5 ns;
X-- --ERROR: MULTIPLE TIME EXPRESSTIONS WITH THE SAME STATIC VALUE IN ONE
X -- WAVEFORM ARE NOT PERMITTED.
X S1 <= '1' after S2, '0' after 2 ns;
X --ERROR: MULTIPLE TIME EXPRESSTIONS WITH THE SAME STATIC VALUE IN ONE
X -- WAVEFORM ARE NOT PERMITTED.
X end process;
X-- end block;
Xend AB_1;
*-*-END-of-e-08-3-0-0010a.vhdl-*-*
echo x - e-08-3-0-0011a.vhdl
sed 's/^X//' >e-08-3-0-0011a.vhdl <<'*-*-END-of-e-08-3-0-0011a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-08-1-4-0011A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that a time expression in a waveform element must be a scalar whose
X-- base type is the the physical type TIME predefined in package STANDARD.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity ENT_1 is
X port (X,Y: in BIT; COUT: out BIT) ;
Xend ENT_1;
X
Xarchitecture AB_1 of ENT_1 is
X-- L_X_1: block
X
X component COMP_1
X generic (P_1 : TIME);
X port (A: in BIT; SOUT: out BIT) ;
X end component ;
X type AR_1 is array (INTEGER range <>) of BOOLEAN;
X signal S1:BIT ;
X signal S3: AR_1 (1 to 10);
X begin
X process
X constant S2: INTEGER := 2;
X begin
X COUT <= S1 after 5;
X --ERROR: THE TIME EXPRESSION IN A WAVEFORM ELEMENT MUST BE A SCALAR WHOSE
X -- BASE TYPE IS THE PHYSICAL TYPE TIME.
X
X S1 <= '1' after S2;
X --ERROR: THE TIME EXPRESSION IN A WAVEFORM ELEMENT MUST BE A SCALAR WHOSE
X -- BASE TYPE IS THE PHYSICAL TYPE TIME.
X
X COUT <= '2' after S3;
X --ERROR: THE TIME EXPRESSION IN A WAVEFORM ELEMENT MUST BE A SCALAR WHOSE
X -- BASE TYPE IS THE PHYSICAL TYPE TIME.
X end process;
X-- end block;
Xend AB_1;
*-*-END-of-e-08-3-0-0011a.vhdl-*-*
echo x - e-08-3-0-0012a.vhdl
sed 's/^X//' >e-08-3-0-0012a.vhdl <<'*-*-END-of-e-08-3-0-0012a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-08-1-4-0012A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that for array signals with static index constraint, even
X-- if the base type are the same the assignment is not permitted
X-- if the number of components are not the same. Check for full
X-- arrays, slices, aggrgates. That is detection of constraint error is by
X-- the analyzer.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
Xend E;
X
Xarchitecture AB of E is
X-- L_X_1: block
X type T is array ( integer range <>) of integer;
X subtype P_array is T( 1 to 50) ;
X subtype I_array is T( 1 to 10) ;
X signal S1: I_array;
X signal S2: I_array;
X signal S3: P_array;
X begin
X process
X begin
X S1 <= S2 ( 1 to 5);
X-- ERROR ARRAY SIGNALS WITH STATIC INDEX CONSTRAINTS ALL COMPONTES MUST BE
X-- UPDATED AT THE SAME TIME.
X
X
X S2 (1 TO 5) <= S1;
X-- ERROR ARRAY SIGNALS WITH STATIC INDEX CONSTRAINTS ALL COMPONTES MUST BE
X-- UPDATED AT THE SAME TIME.
X
X S1 <= S3;
X-- ERROR ARRAY SIGNALS WITH STATIC INDEX CONSTRAINTS ALL COMPONTES MUST BE
X-- UPDATED AT THE SAME TIME.
X
X S3 <= (1 to 10 => 1);
X-- ERROR ARRAY SIGNALS WITH STATIC INDEX CONSTRAINTS ALL COMPONTES MUST BE
X-- UPDATED AT THE SAME TIME.
X
X end process;
X-- end block;
Xend AB;
X
*-*-END-of-e-08-3-0-0012a.vhdl-*-*
echo x - e-08-4-0-0001a.vhdl
sed 's/^X//' >e-08-4-0-0001a.vhdl <<'*-*-END-of-e-08-4-0-0001a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-08-1-5-0001A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the name on the left-hand side which is the target of the
X-- assignment cannot be a unit name (of physical literals), the name of a
X-- package, the name of a subprogram, the name of a design entity, a label,
X-- the name of a body description, the name of a
X-- type or subtype, the name of a component.
X-- JB (DB 7/17/85)
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xuse PACK_1.all ;
Xpackage body PACK_1 is
X function FUN_1 return TIME is
X begin
X return s;
X end FUN_1;
X procedure PROC_1 is
X begin
X null;
X end PROC_1;
Xend PACK_1;
X
X-- with package PACK_1;
Xuse PACK_1.all;
Xentity ENT_1 is
X port (X,Y: in BIT; COUT: out BIT) ;
Xend ENT_1;
X
Xarchitecture BB_1 of ENT_1 is
X-- BL: block
X component COMP_1
X port (A: in BIT; B : out BIT);
X end component ;
X signal S1 : BIT;
X begin
X GEN_1:
X for I in 1 to 1 generate
XL_X_1: block
X begin
X process
X variable B :REAL := 0.1;
X begin
X B := 20.0;
X end process;
X end block;
X end generate GEN_1;
X PL: process
X variable VAR_1:TIME := 0ns;
X variable INIT_1: INTEGER := 1;
X type INT_1 is range 1 to 1000;
X subtype SUBT_1 is INT_1 range 10 to 20;
X begin
X hr := VAR_1;
X --ERROR: A UNIT NAME (OF A PHYSICAL LITERAL) CANNOT BE THE NAME USED ON
X -- THE LEFT-HAND SIDE OF A VARIABLE ASSIGNMENT
X LOOP_1:
X for i in 1 to 1 loop
X INIT_1 := INIT_1 + 1;
X end loop LOOP_1;
X LOOP_1 := INIT_1;
X --ERROR: A LOOP LABEL CANNOT BE THE NAME USED ON
X -- THE LEFT-HAND SIDE OF A VARIABLE ASSIGNMENT
X PACK_1 := INIT_1;
X --ERROR: A PACKAGE NAME CANNOT BE THE NAME USED ON
X -- THE LEFT-HAND SIDE OF A VARIABLE ASSIGNMENT
X FUN_1 := VAR_1;
X --ERROR: A FUNCTION NAME CANNOT BE THE NAME USED ON
X -- THE LEFT-HAND SIDE OF A VARIABLE ASSIGNMENT
X PROC_1 := INIT_1;
X --ERROR: A PROCEDURE NAME CANNOT BE THE NAME USED ON
X -- THE LEFT-HAND SIDE OF A VARIABLE ASSIGNMENT
X ENT_1 := INIT_1;
X --ERROR: A DESIGN ENTITY NAME CANNOT BE THE NAME USED ON
X -- THE LEFT-HAND SIDE OF A VARIABLE ASSIGNMENT
X BB_1 := INIT_1;
X --ERROR: A BODY DECLARATION NAME CANNOT BE THE NAME USED ON
X -- THE LEFT-HAND SIDE OF A VARIABLE ASSIGNMENT
X INT_1 := VAR_1;
X --ERROR: A TYPE NAME CANNOT BE THE NAME USED ON
X -- THE LEFT-HAND SIDE OF A VARIABLE ASSIGNMENT
X SUBT_1 := VAR_1;
X --ERROR: A SUBTYPE NAME CANNOT BE THE NAME USED ON
X -- THE LEFT-HAND SIDE OF A VARIABLE ASSIGNMENT
X GEN_1 := INIT_1;
X --ERROR: A GENERATE LABEL CANNOT BE THE NAME USED ON
X -- THE LEFT-HAND SIDE OF A VARIABLE ASSIGNMENT
X COMP_1 := INIT_1;
X --ERROR: A COMPONENT NAME CANNOT BE THE NAME USED ON
X -- THE LEFT-HAND SIDE OF A VARIABLE ASSIGNMENT
X C1 := INIT_1;
X --ERROR: A COMPONENT LABEL CANNOT BE THE NAME USED ON
X -- THE LEFT-HAND SIDE OF A VARIABLE ASSIGNMENT
X BL := INIT_1;
X --ERROR: A BLOCK LABEL CANNOT BE THE NAME USED ON
X -- THE LEFT-HAND SIDE OF A VARIABLE ASSIGNMENT
X PL := INIT_1;
X --ERROR: A PROCESS LABEL CANNOT BE THE NAME USED ON
X -- THE LEFT-HAND SIDE OF A VARIABLE ASSIGNMENT
X end process;
X-- end block;
Xend BB_1;
*-*-END-of-e-08-4-0-0001a.vhdl-*-*
echo x - e-08-4-0-0002a.vhdl
sed 's/^X//' >e-08-4-0-0002a.vhdl <<'*-*-END-of-e-08-4-0-0002a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-08-1-5-0002A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the left-hand side which is the target of the assignment cannot be
X-- a literal (enumeration, numeric, physical, string).
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
X
Xentity ENT_1 is
X port (X,Y: in BIT; COUT: out BIT) ;
Xend ENT_1;
X
Xarchitecture BB_1 of ENT_1 is
X-- L_X_1: block
X begin
X process
X variable VAR_1: BIT := '1';
X begin
X LOW := VAR_1;
X --ERROR: AN ENUMERATION LITERAL CANNOT BE THE NAME USED ON THE LEFT-HAND
X -- SIDE OF A VARIABLE ASSIGNMENT
X
X min := VAR_1;
X --ERROR: A PHYSICAL LITERAL CANNOT BE THE NAME USED ON THE LEFT-HAND
X -- SIDE OF A VARIABLE ASSIGNMENT
X
X 60 min := VAR_1;
X --ERROR: A NUMERIC LITERAL CANNOT BE THE NAME USED ON THE LEFT-HAND
X -- SIDE OF A VARIABLE ASSIGNMENT
X
X '0' := VAR_1;
X --ERROR: AN ENUMERATION LITERAL CANNOT BE THE NAME USED ON THE LEFT-HAND
X -- SIDE OF A VARIABLE ASSIGNMENT
X
X 0.0 := VAR_1;
X --ERROR: A NUMERIC LITERAL CANNOT BE THE NAME USED ON THE LEFT-HAND
X -- SIDE OF A VARIABLE ASSIGNMENT
X
X 2#111# := VAR_1;
X --ERROR: A NUMERIC LITERAL CANNOT BE THE NAME USED ON THE LEFT-HAND
X -- SIDE OF A VARIABLE ASSIGNMENT
X
X "LITERAL" := VAR_1;
X --ERROR: A STRING LITERAL CANNOT BE THE NAME USED ON THE LEFT-HAND
X -- SIDE OF A VARIABLE ASSIGNMENT
X end process;
X-- end block;
Xend BB_1;
*-*-END-of-e-08-4-0-0002a.vhdl-*-*
echo x - e-08-4-0-0003a.vhdl
sed 's/^X//' >e-08-4-0-0003a.vhdl <<'*-*-END-of-e-08-4-0-0003a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-08-1-5-0003A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the left-hand side which is the target of the assignment cannot be
X-- an aggregate or a slice of an aggregate.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity ENT_1 is
X port (X,Y: in BIT; COUT: out BIT) ;
Xend ENT_1;
X
Xarchitecture AB_1 of ENT_1 is
X-- L_X_1: block
X component COMP_1 port (A: in BIT; SOUT: out BIT);
X end component ;
X type AR_1 is array (INTEGER range <>) of BOOLEAN;
X subtype ARAY is AR_1 (1 to 10);
X type REC_1 is record
X RE_1 : INTEGER;
X RE_2 : BOOLEAN;
X end record;
X begin
X process
X variable V1:BIT := '1';
X variable V2: ARAY;
X variable V3: REC_1;
X variable V4: ARAY;
X variable V5: REC_1;
Xbegin
X (RE_1 => 2) <= 2 after 2 ns;
X --ERROR: AGGREGATES CANNOT BE A TARGET ON THE LEFT-HAND SIDE OF
X -- A VARIABLE ASSIGNMENT
X
X (1, 5, 9, 2) <= 2 after 2 ns;
X --ERROR: AGGREGATES CANNOT BE A TARGET ON THE LEFT-HAND SIDE OF
X -- A VARIABLE ASSIGNMENT
X
X (others => FALSE) <= 2 after 2 ns;
X --ERROR: AGGREGATES CANNOT BE A TARGET ON THE LEFT-HAND SIDE OF
X -- A VARIABLE ASSIGNMENT
X end process;
X-- end block;
Xend AB_1;
*-*-END-of-e-08-4-0-0003a.vhdl-*-*
echo x - e-08-4-0-0004a.vhdl
sed 's/^X//' >e-08-4-0-0004a.vhdl <<'*-*-END-of-e-08-4-0-0004a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-08-1-5-0004A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the left-hand side which is the target of the assignment cannot be
X-- an expression (other than an expression which is a simple name, an indexed
X-- name, a selected name, a slice name).
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xpackage PACK_1 is
X function FUN_1 return BOOLEAN ;
Xend PACK_1 ;
X
Xpackage body PACK_1 is
X function FUN_1 return BOOLEAN is
X begin
X return FALSE;
X end FUN_1;
Xend PACK_1;
X
X
X-- with package PACK_1;
Xuse PACK_1.all;
Xentity ENT_1 is
X port (X,Y: in BIT; COUT: out BIT) ;
Xend ENT_1;
X
Xarchitecture BB_1 of ENT_1 is
X-- L_X_1: block
X begin
X process
X type ENUM_1 is (ONE,TWO,THREE);
X type ENUM_2 is (ONE,THREE,FIVE);
X type INIT_1 is range 16#1# to 16#FF#;
X variable V1,V2,V3: BIT;
X variable V4: ENUM_1 := ONE;
X variable V5: INTEGER := 5;
X begin
X V1 + V2 := V3;
X --ERROR: RELATIONAL EXPRESSIONS ARE NOT ALLOWED ON THE LEFT-HAND SIDE
X -- OF A VARIABLE ASSIGNMENT
X
X V2 and V3 := V1;
X --ERROR: LOGICAL EXPRESSIONS ARE NOT ALLOWED ON THE LEFT-HAND SIDE
X -- OF A VARIABLE ASSIGNMENT
X
X V5**2 := V5;
X --ERROR: SIMPLE EXPRESSIONS ARE NOT ALLOWED ON THE LEFT-HAND SIDE
X -- OF A VARIABLE ASSIGNMENT
X
X abs V5 := V5;
X --ERROR: SIMPLE EXPRESSIONS ARE NOT ALLOWED ON THE LEFT-HAND SIDE
X -- OF A VARIABLE ASSIGNMENT
X
X 5.2E3 := V5;
X --ERROR: LITERALS ARE NOT ALLOWED ON THE LEFT-HAND SIDE
X -- OF A VARIABLE ASSIGNMENT
X
X TWO - ONE := V5;
X --ERROR: LITERALS ARE NOT ALLOWED ON THE LEFT-HAND SIDE
X -- OF A VARIABLE ASSIGNMENT
X
X FUN_1 := V1;
X --ERROR: FUNCTION CALLS ARE NOT ALLOWED ON THE LEFT-HAND SIDE
X -- OF A VARIABLE ASSIGNMENT
X
X INIT_1(V5) := V5;
X --ERROR: TYPE CONVERSIONS ARE NOT ALLOWED ON THE LEFT-HAND SIDE
X -- OF A VARIABLE ASSIGNMENT
X
X ENUM_1'(V4) := V4;
X --ERROR: QUALIFIED EXPRESSIONS ARE NOT ALLOWED ON THE LEFT-HAND SIDE
X -- OF A VARIABLE ASSIGNMENT
X
X return;
X end process;
X-- end block;
Xend BB_1;
*-*-END-of-e-08-4-0-0004a.vhdl-*-*
echo x - e-08-4-0-0005a.vhdl
sed 's/^X//' >e-08-4-0-0005a.vhdl <<'*-*-END-of-e-08-4-0-0005a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-08-1-5-0005A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the name on the left-hand side which is the target of the
X-- assignment cannot be a signal, an attribute, an input parameter of a function, a
X-- constant, or a generic parameter, or an alias of any of these.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
X
Xpackage PACK_1 is
X function FUN_2 (PAR_2:BIT := '1') return BIT ;
Xend PACK_1 ;
Xpackage body PACK_1 is
X
X function FUN_2 (PAR_2:BIT := '1') return BIT is
X variable VAR_1: BIT := '0';
X begin
X PAR_2 := VAR_1;
X --ERROR: AN INPUT PARAMETER OF A FUNCTION CANNOT BE THE NAME USED ON THE
X -- LEFT-HAND SIDE OF A VARIABLE ASSIGNMENT
X
X return VAR_1;
X end FUN_2;
Xend PACK_1;
X
Xentity ENT_1 is
X generic (PARM_A: TIME := 3 ns) ;
X port (X,Y: in BIT; COUT: out BIT) ;
X
X type AR_1 is array (1 to 10) of BIT;
X constant VAR_3 : BIT := '1';
X
X alias ALIAN_E1: TIME is PARM_A;
X alias ALIAN_E2: BIT is COUT;
X alias ALIAN_E3: BIT is VAR_3;
Xend ENT_1;
X
Xarchitecture BB_1 of ENT_1 is
X-- L_X_1: block
X begin
X process
X variable VAR_1: INTEGER;
X variable VAR_2: BIT := '0';
X
X begin
X COUT := VAR_2;
X --ERROR: A SIGNAL (PORT) NAME CANNOT BE THE NAME USED ON THE LEFT-HAND
X -- SIDE OF A VARIABLE ASSIGNMENT
X
X ALIAN_E2 := VAR_2;
X --ERROR: AN ALIAS OF A SIGNAL (PORT) NAME CANNOT BE THE NAME USED ON THE
X -- LEFT-HAND SIDE OF A VARIABLE ASSIGNMENT
X
X VAR_3 := VAR_1;
X --ERROR: A CONSTANT VARIABLE CANNOT BE THE NAME OF THE LEFT-HAND
X -- SIDE OF A VARIABLE ASSIGNMENT
X
X ALIAN_E3 := VAR_1;
X --ERROR: AN ALIAS OF A CONSTANT VARIABLE CANNOT BE THE NAME ON THE LEFT-HAND
X -- SIDE OF A VARIABLE ASSIGNMENT
X
X AR_1'LOW := S1;
X --ERROR: AN ATTRIBUTE CANNOT BE THE NAME USED ON THE LEFT-HAND
X -- SIDE OF A VARIABLE ASSIGNMENT
X
X PARM_A := S1;
X --ERROR: A GENERIC PARAMETER CANNOT BE THE NAME USED ON THE LEFT-HAND
X -- SIDE OF A VARIABLE ASSIGNMENT
X
X ALIAN_E1 := S1;
X --ERROR: AN ALIAS OF A GENERIC PARAMETER CANNOT BE THE NAME USED ON THE
X -- SIDE OF A VARIABLE ASSIGNMENT
X end process;
X-- end block;
Xend BB_1;
*-*-END-of-e-08-4-0-0005a.vhdl-*-*
echo x - e-08-4-0-0006a.vhdl
sed 's/^X//' >e-08-4-0-0006a.vhdl <<'*-*-END-of-e-08-4-0-0006a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-08-1-5-0006A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that multiple left-hand side variables are not permitted (analogy to
X-- signal assignment statement).
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity ENT_1 is
X port (PT: BOOLEAN) ;
Xend ENT_1;
X
Xarchitecture BB_1 of ENT_1 is
X-- L_X_1: block
X begin
X process
X type ARAY_1 is array (INTEGER range <>) of INTEGER;
X subtype SAR_1 is ARAY_1 (1 to 10);
X variable VAR_1, VAR_2, VAR_3: INTEGER;
X variable VAR_4, VAR_5: SAR_1;
X begin
X ( VAR_1, VAR_2, VAR_3 ) := 5;
X
X VAR_1, VAR_2, VAR_3 := 5;
X --ERROR: MULTIPLE VARIABLES ON THE LEFT-HAND SIDE OF A VARIABLE ASSIGNMENT
X -- IS NOT PERMITTED
X
X ( VAR_4(5), VAR_5(5) ) := VAR_1;
X
X VAR_4(5), VAR_5(5) := VAR_1;
X --ERROR: MULTIPLE VARIABLES ON THE LEFT-HAND SIDE OF A VARIABLE ASSIGNMENT
X -- IS NOT PERMITTED
X
X end process;
X-- end block;
Xend BB_1;
*-*-END-of-e-08-4-0-0006a.vhdl-*-*
echo x - e-08-4-0-0007a.vhdl
sed 's/^X//' >e-08-4-0-0007a.vhdl <<'*-*-END-of-e-08-4-0-0007a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-08-1-5-0007A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the subtype of an expression on the right-hand side must be the
X-- same as or convertable to the base type of the object on the left-hand side
X-- to which it is being assigned.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity ENT_1 is
X port (PT: BOOLEAN) ;
Xend ENT_1;
X
Xarchitecture BB_1 of ENT_1 is
X-- L_X_1: block
X begin
X process
X type ARAY_1 is array (1 to 10) of BIT;
X type ARAY_2 is array (1 to 10) of CHARACTER;
X variable VAR_1: INTEGER := 5;
X variable VAR_2: BOOLEAN := FALSE;
X variable VAR_3: ARAY_1;
X variable VAR_4: ARAY_2;
X begin
X VAR_1 := VAR_2;
X --ERROR: THE BASE TYPE OF THE EXPRESSION ON THE RIGHT-HAND SIDE MUST BE
X -- THE SAME AS THE BASE TYPE OF THE OBJECT ON THE LEFT-HAND SIDE OF THE
X -- ASSIGNMENT
X
X VAR_2 := VAR_3(4);
X --ERROR: THE BASE TYPE OF THE EXPRESSION ON THE RIGHT-HAND SIDE MUST BE
X -- THE SAME AS THE BASE TYPE OF THE OBJECT ON THE LEFT-HAND SIDE OF THE
X -- ASSIGNMENT
X
X VAR_3(4) := VAR_1;
X --ERROR: THE BASE TYPE OF THE EXPRESSION ON THE RIGHT-HAND SIDE MUST BE
X -- THE SAME AS THE BASE TYPE OF THE OBJECT ON THE LEFT-HAND SIDE OF THE
X -- ASSIGNMENT
X
X VAR_3 := VAR_4;
X --ERROR: THE BASE TYPE OF THE EXPRESSION ON THE RIGHT-HAND SIDE MUST BE
X -- THE SAME AS THE BASE TYPE OF THE OBJECT ON THE LEFT-HAND SIDE OF THE
X -- ASSIGNMENT
X end process;
X-- end block;
Xend BB_1;
*-*-END-of-e-08-4-0-0007a.vhdl-*-*
echo x - e-08-4-0-0008a.vhdl
sed 's/^X//' >e-08-4-0-0008a.vhdl <<'*-*-END-of-e-08-4-0-0008a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-08-1-5-0008A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the right-hand side of a variable assignment statement cannot be a
X-- waveform.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xuse P.all;
Xpackage P is
Xfunction FUN_1 return BOOLEAN ;
Xend P ;
X
Xuse P.all ;
Xpackage body P is
Xfunction FUN_1 return BOOLEAN is
X variable VAR_1, VAR_2: INTEGER;
Xbegin
X VAR_1 := VAR_2 after 3 ns;
X --ERROR: THE RIGHT-HAND SIDE EXPRESSION OF A VARIABLE ASSIGNMENT CANNOT BE
X -- A WAVEFORM.
X end FUN_1;
Xend P ;
X
Xentity ENT_1 is
X port (PT: BOOLEAN) ;
Xend ENT_1;
X
Xarchitecture BB_1 of ENT_1 is
X-- L_X_1: block
X begin
X process
X variable VAR_1, VAR_2: INTEGER;
X begin
X VAR_1 := VAR_2 after 3 ns;
X --ERROR: THE RIGHT-HAND SIDE EXPRESSION OF A VARIABLE ASSIGNMENT CANNOT BE
X -- A WAVEFORM.
X end process;
X-- end block;
Xend BB_1;
*-*-END-of-e-08-4-0-0008a.vhdl-*-*
echo x - e-08-4-1-1001a.vhdl
sed 's/^X//' >e-08-4-1-1001a.vhdl <<'*-*-END-of-e-08-4-1-1001a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-08-1-5-1001A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that for array variables of static index constraints, even if the
X-- base type are the same the assignment is not permitted if the number of
X-- components are not the same. Check for full arrays, slices, aggregates.
X-- That is, detection of constraint error is by analyzer.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
X
Xpackage PACK_1 is
X type MY_ARRAY is array (INTEGER range <>) of BIT;
X subtype MY_BIT is MY_ARRAY (1 to 7);
Xend PACK_1;
X
X-- with package PACK_1;
Xuse PACK_1.all;
Xentity ENT_1 is
X port (X,Y: in BIT_VECTOR; Z: inout MY_BIT;
X COUT: out BIT_VECTOR) ;
Xend ENT_1;
X
Xarchitecture BB_1 of ENT_1 is
X-- L_X_1: block
X begin
X process
X type ARAY_1 is array (INTEGER range <>) of BIT;
X subtype SUB_ONE is ARAY_1 (1 to 10);
X subtype SUB_TWO is ARAY_1 (1 to 100);
X subtype SUB_THREE is ARAY_1 (41 to 60);
X variable V1: SUB_ONE;
X variable V2: SUB_TWO;
X variable V3: SUB_THREE;
X begin
X V1 := V3;
X--ERROR NUMBER OF COMPONENTS ARE NOT EQUAL
X V3 := V2(1to 40);
X--ERROR NUMBER OF COMPONENTS ARE NOT EQUAL
X V2(50 to 90) := V1;
X--ERROR NUMBER OF COMPONENTS ARE NOT EQUAL
X V1(20 to 25) := V2(1 to 100);
X--ERROR NUMBER OF COMPONENTS ARE NOT EQUAL
X V1 := (1 to 9 => '1');
X--ERROR NUMBER OF COMPONENTS ARE NOT EQUAL
X end process;
X-- end block;
Xend BB_1;
X
X
*-*-END-of-e-08-4-1-1001a.vhdl-*-*
echo x - e-08-5-0-0001a.vhdl
sed 's/^X//' >e-08-5-0-0001a.vhdl <<'*-*-END-of-e-08-5-0-0001a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-08-1-6-0001A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that in a procedure call the type of each argument in the argument
X-- list must be compatible with the type of the corresponding input parameter
X-- in the definition of the procedure. Check for postional inversion of
X-- arguments.
X-- JB (DB 7/12/85)
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
X
Xpackage P is
X type ENUM is ( ONE, TWO, THREE, FOUR );
X type NEW_INTEGER is range INTEGER'low to INTEGER'high;
X type SNACK is
X range 1 to 1e18
X units
X fn; -- figanewton
X bf = 144 fn; -- boxafiganewton
X end units;
X type UN_ARRAY is array ( ENUM range <> ) of CHARACTER;
X subtype SMALL_ARRAY is UN_ARRAY ( TWO to THREE );
X subtype LARGE_ARRAY is UN_ARRAY ( TWO to FOUR );
X type A_RECORD is record
X E : BIT;
X end record;
X type B_RECORD is record
X E : BIT;
X end record;
X
X procedure F_ENUM (A : ENUM := ONE; B : ENUM := TWO ) ;
X
X procedure F_NEW (A : INTEGER; B : NEW_INTEGER ) ;
X
X procedure F_SNACK ( A : REAL := 1.0; B : NEW_INTEGER; C : SNACK ) ;
X
X procedure F_UN (A : UN_ARRAY; B : CHARACTER ) ;
X
X procedure F_SMALL (A : SMALL_ARRAY ) ;
X
X procedure F_AREC (A : A_RECORD; B : B_RECORD ) ;
X
X procedure F_REAL ( A,B,C,D : REAL ) ;
X
Xend P;
Xpackage body P is
X
X procedure F_ENUM (A : ENUM := ONE; B : ENUM := TWO ) is
X begin
X null;
X end F_ENUM;
X
X procedure F_NEW (A : INTEGER; B : NEW_INTEGER ) is
X begin
X return;
X end F_NEW;
X
X procedure F_SNACK ( A : REAL := 1.0; B : NEW_INTEGER; C : SNACK ) is
X begin
X null;
X end F_SNACK;
X
X procedure F_UN (A : UN_ARRAY; B : CHARACTER ) is
X begin
X return;
X end F_UN;
X
X procedure F_SMALL (A : SMALL_ARRAY ) is
X begin
X null;
X end F_SMALL;
X
X procedure F_AREC (A : A_RECORD; B : B_RECORD ) is
X begin
X return;
X end F_AREC;
X
X procedure F_REAL ( A,B,C,D : REAL ) is
X begin
X null;
X end F_REAL;
X
Xend P;
X
X-- with package P;
Xuse P.all;
Xpackage P is
Xfunction WHATEVER ( A,B : INTEGER ) return INTEGER ;
Xend P ;
X
X-- with package P;
Xuse P.all;
Xpackage body P is
Xfunction WHATEVER ( A,B : INTEGER ) return INTEGER is
Xbegin
X F_NEW(A,B);
X -- SEMANTIC ERROR: type of second argument incompatible with type of
X -- parameter.
X return 23;
X end WHATEVER;
X end P ;
X
Xpackage P is
Xprocedure P2 ;
Xend P ;
X
Xuse P.all ;
Xpackage body P is
Xprocedure P2 is
Xbegin
X F_NEW(A=>NEW_INTEGER'(1),B=>INTEGER'(2));
X -- SEMANTIC ERROR: types of arguments incompatible with types of
X -- parameters.
X end P2;
Xend P ;
X
X-- with package P;
Xuse P.all;
Xentity E is
X port ( PT1 : in A_RECORD; PT2 : out A_RECORD ) ;
Xend E;
X
Xarchitecture BB of E is
X-- L_X_1: block
X begin
X process
X variable A : SMALL_ARRAY;
X begin
X for CHAR in CHARACTER'LEFT to CHARACTER'RIGHT loop
X F_UN( CHAR, A );
X -- SEMANTIC ERROR: types of arguments incompatible with
X -- types of parameters.
X end loop;
X return;
X end process;
X-- end block;
Xend BB;
X
X-- with package P;
Xuse P.all;
Xarchitecture AB of E is
X-- L_X_2: block
X begin
X process
X begin
X F_AREC(PT1,PT1);
X -- SEMANTIC ERROR: type of second argument incompatible with type of
X -- parameter.
X end process;
X-- end block;
Xend AB;
*-*-END-of-e-08-5-0-0001a.vhdl-*-*
echo x - e-08-6-0-0001a.vhdl
sed 's/^X//' >e-08-6-0-0001a.vhdl <<'*-*-END-of-e-08-6-0-0001a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-08-1-7-0001A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that an expression specifying a condition in an if statement must be of
X-- a boolean type.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xpackage PACK_1 is
X function FUN_2 return BIT ;
Xend PACK_1;
X
Xuse PACK_1.all ;
Xpackage body PACK_1 is
X function FUN_2 return BIT is
X variable VAR_1: BIT;
X variable RESULT : BIT := '1';
X begin
X return RESULT;
X end FUN_2;
Xend PACK_1;
X
X-- with package PACK_1;
Xuse PACK_1.all;
Xpackage PACK_1 is
Xfunction FUN_1 return BOOLEAN ;
Xend PACK_1 ;
X
Xuse PACK_1.all ;
Xpackage body PACK_1 is
Xfunction FUN_1 return BOOLEAN is
X variable VAR_1: INTEGER;
X variable VAR_2: BOOLEAN;
X variable VAR_3: INTEGER;
Xbegin
X if VAR_1 + 2 then
X --ERROR: THE CONDITION EXPRESSION MUST BE OF A BOOLEAN TYPE
X return FALSE;
X end if;
X
X if VAR_1 and VAR_3 then
X --ERROR: THE CONDITION EXPRESSION MUST BE OF A BOOLEAN TYPE
X return TRUE;
X end if;
X
X if VAR_3**2 then
X --ERROR: THE CONDITION EXPRESSION MUST BE OF A BOOLEAN TYPE
X return FALSE;
X end if;
X
X if FUN_2 then
X --ERROR: THE CONDITION EXPRESSION MUST BE OF A BOOLEAN TYPE
X return FALSE;
X end if;
X
X return TRUE;
X end FUN_1;
Xend PACK_1 ;
*-*-END-of-e-08-6-0-0001a.vhdl-*-*
echo x - e-08-6-0-0002a.vhdl
sed 's/^X//' >e-08-6-0-0002a.vhdl <<'*-*-END-of-e-08-6-0-0002a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-08-1-7-0002A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that an if statement must end with an "end if".
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xuse P.all ;
Xpackage P is
Xfunction F return BOOLEAN ;
Xend P ;
X
Xuse P.all ;
Xpackage body P is
Xfunction F return BOOLEAN is
X variable VAR_1: INTEGER := 5;
X variable VAR_2: INTEGER;
X variable VAR_3: BOOLEAN := TRUE;
Xbegin
X if VAR_1 > 7 then
X VAR_3 := FALSE;
X else
X VAR_2 := 1;
X return false;
X end F
X --ERROR: AN IF STATEMENT MUST END WITH AN "END IF"
X;
Xend P ;
X
*-*-END-of-e-08-6-0-0002a.vhdl-*-*
echo x - e-08-6-0-0003a.vhdl
sed 's/^X//' >e-08-6-0-0003a.vhdl <<'*-*-END-of-e-08-6-0-0003a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-08-1-7-0003A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the else of an enclosing if statement cannot be used to terminate
X-- a nested if statement.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
X-------------------------------------------------------------------------------
X-- Because of the way the syntax checker evaluates the end of an if statement,
X-- the second behavioral body in this test is not correctly evaluated. This
X-- second body is tested independently in test case E7400003B.
X-------------------------------------------------------------------------------
X
Xentity ENT_1 is
X port (PT: BOOLEAN) ;
Xend ENT_1;
X
Xarchitecture BB_1 of ENT_1 is
X-- L_X_1: block
X begin
X process
X variable VAR_1: INTEGER :=3;
X variable VAR_2: INTEGER;
X variable VAR_3: BOOLEAN;
X begin
X if VAR_1 > 4 then
X if VAR_2 < 4 then
X VAR_3 := TRUE;
X else
X VAR_3 := FALSE;
X end if;
X end process;
X --ERROR: AN ELSE OF AN ENCLOSING IF STATEMENT CANNOT BE USED TO TERMINATE
X -- A NESTED IF STATEMENT
X-- end block;
Xend BB_1;
X
Xarchitecture BB_2 of ENT_1 is
X-- L_X_2: block
X begin
X process
X variable VAR_1: INTEGER :=3;
X variable VAR_2: INTEGER;
X variable VAR_3: BOOLEAN;
X begin
X if VAR_1 > 4 then
X if VAR_2 < 4 then
X VAR_3 := TRUE;
X else
X VAR_2 := 4;
X else
X --ERROR: AN ELSE OF AN ENCLOSING IF STATEMENT CANNOT BE USED TO TERMINATE
X -- A NESTED IF STATEMENT
X VAR_3 := FALSE;
X end if;
X end process;
X-- end block;
Xend BB_2;
*-*-END-of-e-08-6-0-0003a.vhdl-*-*
echo x - e-08-6-0-0003b.vhdl
sed 's/^X//' >e-08-6-0-0003b.vhdl <<'*-*-END-of-e-08-6-0-0003b.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-08-1-7-0003B.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the else of an enclosing if statement cannot be used to terminate
X-- a nested if statement.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity ENT_1 is
X port (PT: BOOLEAN) ;
Xend ENT_1;
X
Xarchitecture BB_2 of ENT_1 is
X-- L_X_1: block
X begin
X process
X variable VAR_1: INTEGER :=3;
X variable VAR_2: INTEGER;
X variable VAR_3: BOOLEAN;
X begin
X if VAR_1 > 4 then
X if VAR_2 < 4 then
X VAR_3 := TRUE;
X else
X VAR_2 := 4;
X else
X --ERROR: AN ELSE OF AN ENCLOSING IF STATEMENT CANNOT BE USED TO TERMINATE
X -- A NESTED IF STATEMENT
X VAR_3 := FALSE;
X end if;
X end process;
X-- end block;
Xend BB_2;
*-*-END-of-e-08-6-0-0003b.vhdl-*-*
echo x - e-08-6-0-0004a.vhdl
sed 's/^X//' >e-08-6-0-0004a.vhdl <<'*-*-END-of-e-08-6-0-0004a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-08-1-7-0004A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that else cannot precede elsif in an if statement (check when no elsif
X-- precedes the else).
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity ENT_1 is
X port (PT: BOOLEAN) ;
Xend ENT_1;
X
Xarchitecture BB_1 of ENT_1 is
X-- L_X_1: block
X begin
X process
X variable VAR_1: INTEGER :=3;
X variable VAR_2: INTEGER;
X variable VAR_3: BOOLEAN;
X begin
X if VAR_1 > 4 then
X if VAR_2 < 4 then
X VAR_3 := TRUE;
X end if;
X else
X VAR_3 := FALSE;
X elsif VAR_1 < 4 then
X --ERROR: AN ELSE CANNOT PRECEDE AN ELSIF IN AN IF STATEMENT
X VAR_2 := 4;
X end if;
X end process;
X-- end block;
Xend BB_1;
*-*-END-of-e-08-6-0-0004a.vhdl-*-*
echo x - e-08-6-0-0005a.vhdl
sed 's/^X//' >e-08-6-0-0005a.vhdl <<'*-*-END-of-e-08-6-0-0005a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-08-1-7-0005A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that else cannot precede elsif in an if statement (check when else if
X-- preceded by elsif).
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity ENT_1 is
X port (PT: BOOLEAN) ;
Xend ENT_1;
X
Xarchitecture BB_1 of ENT_1 is
X-- L_X_1: block
X begin
X process
X variable VAR_1: INTEGER :=3;
X variable VAR_2: INTEGER;
X variable VAR_3: BOOLEAN;
X begin
X if VAR_1 > 4 then
X if VAR_2 < 4 then
X VAR_3 := TRUE;
X end if;
X elsif VAR_1 = 4 then
X VAR_2 := 0;
X else
X VAR_3 := FALSE;
X elsif VAR_1 < 4 then
X --ERROR: AN ELSE CANNOT PRECEDE AN ELSIF IN AN IF STATEMENT
X VAR_2 := 4;
X end if;
X end process;
X-- end block;
Xend BB_1;
X
*-*-END-of-e-08-6-0-0005a.vhdl-*-*
echo x - e-08-7-0-0001a.vhdl
sed 's/^X//' >e-08-7-0-0001a.vhdl <<'*-*-END-of-e-08-7-0-0001a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-08-1-8-0001A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the expression in a case statement must be of a discrete type.
X-- Special cases: check that the expression cannot be a string or floating point
X-- type.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xpackage P is
X type PH is range 1 to 24
X units
X U;
X X = 3U;
X Y = 2X;
X end units;
X function F return BOOLEAN ;
Xend P;
X
Xuse P.all ;
Xpackage body P is
X function F return BOOLEAN is
X variable V : PH := X;
X begin
X case V is -- ERROR : case expression not of discrete type
X when U to 4Y => return TRUE;
X end case;
X end F;
Xend P;
X
Xentity E is
X port (PT:inout REAL) ;
Xend E;
X
Xarchitecture BB of E is
X-- L_X_1: block
X begin
X process
X variable V1,V2 : STRING (1 to 4) := "OHNO";
X begin
X case V1(1) & V2(4) is -- ERROR : case expression not of discrete type
X when "OO" => return;
X when others => return;
X end case;
X
X case PT - 9.989 is -- ERROR : case expression not of discrete type
X when others => PT <= 0.0;
X end case;
X
X end process;
X-- end block;
Xend BB;
*-*-END-of-e-08-7-0-0001a.vhdl-*-*
echo x - e-08-7-0-0002a.vhdl
sed 's/^X//' >e-08-7-0-0002a.vhdl <<'*-*-END-of-e-08-7-0-0002a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-08-1-8-0002A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that each choice in a case statement alternative must be of the same
X-- type as the expression.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xpackage P is
X type E is (A,B,C,D);
X function F return BOOLEAN ;
Xend P;
X
Xuse P.all ;
Xpackage body P is
X function F return BOOLEAN is
X variable V : E := C;
X begin
X case V is
X when A | C => return TRUE;
X when D |'D' => return FALSE; -- ERROR : case choice of wrong type
X when others => return TRUE;
X end case;
X end F;
Xend P;
X
Xentity E is
X port (PT:inout REAL) ;
Xend E;
X
Xarchitecture BB of E is
X-- L_X_1: block
X begin
X process
X type E1 is (ONE,TWO);
X type E2 is (ONE,TWO);
X variable V1,V2 : BOOLEAN := TRUE;
X begin
X case V1 or V2 is
X when TRUE | 0 => return; -- ERROR : case choice of wrong type
X when others => return;
X end case;
X
X case E1'(ONE) is
X when E2'(ONE) => PT <= 0.1; -- ERROR : case choice of wrong type
X when others => PT <= 0.0;
X end case;
X
X end process;
X-- end block;
Xend BB;
X
*-*-END-of-e-08-7-0-0002a.vhdl-*-*
echo x - e-08-7-0-0003a.vhdl
sed 's/^X//' >e-08-7-0-0003a.vhdl <<'*-*-END-of-e-08-7-0-0003a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-08-1-8-0003A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that if the subtype of the expression is not statically determinable
X-- then each value of the base type of the expression must be represented once
X-- and only once in the set of choices of the case statement. Special case:
X-- Check that a choice defined by a discrete range stands for all values in the
X-- corresponding range. Special case: Check that two choices with overlapping
X-- discrete ranges are not allowed.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xpackage P is
X function F (P1:NATURAL) return BOOLEAN ;
Xend P;
X
Xuse P.all ;
Xpackage body P is
X function F (P1:NATURAL) return BOOLEAN is
X subtype ST is CHARACTER range ' ' to CHARACTER'VAL(P1);
X variable V : ST;
X begin
X V := ST'VAL(P1);
X case ST'PRED(V) is
X when 'A' to 'C' => return TRUE;
X when 'A' => return FALSE; -- ERROR : choice already represented
X when 'B' => return FALSE; -- ERROR : choice already represented
X when 'C' => return FALSE; -- ERROR : choice already represented
X when others => return TRUE;
X end case;
X end F;
Xend P;
X
Xentity E is
X generic (G:INTEGER) ;
X port (PT:inout REAL) ;
X
Xend E;
X
Xarchitecture BB of E is
X-- L_X_1: block
X begin
X process
X subtype ST is INTEGER range G to -G;
X variable V : ST := 0;
X variable V1 : static POSITIVE := 1;
X variable V2,V3 : ST := 1;
X begin
X case V3 * V2 is
X when 25 to 45 => return;
X when 0 to 30 => return; -- ERROR : overlaps other choice rang
X when others => return;
X end case;
X
X case - V is
X when 0 downto -5 => PT <= 0.9;
X when 5 downto 0 => PT <= 1.1; -- ERROR : overlaps other choice rang
X end case; -- ERROR : parts of base type not represented
X
X end process;
X-- end block;
Xend BB;
*-*-END-of-e-08-7-0-0003a.vhdl-*-*
echo x - e-08-7-0-0004a.vhdl
sed 's/^X//' >e-08-7-0-0004a.vhdl <<'*-*-END-of-e-08-7-0-0004a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-08-1-8-0004A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that if the expression is the name of an object whose subtype is
X-- statically determinable or a qualified expression whose type mark denotes
X-- a static subtype then each value of the subtype must be represented once
X-- and only once in the set of choices of the case statement. Special case:
X-- check for qualified expressions and names of objects of static subtype.
X-- Special case: Check that a choice defined by a discrete range stands
X-- for all values in the corresponding range. Special case: Check that
X-- two choices with overlapping discrete ranges are not allowed.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xpackage P is
X function F return BOOLEAN ;
Xend P;
X
Xuse P.all ;
Xpackage body P is
X function F return BOOLEAN is
X type I1 is range 0 to 10;
X variable V1 : I1 := 6;
X begin
X case V1 is
X when 0 to 5 => return TRUE;
X when 5 to 10 => return FALSE; -- ERROR : choice already represente
X end case;
X end F;
Xend P;
X
Xuse P.all ;
Xpackage P is
X function F return REAL ;
Xend P ;
X
Xuse P.all ;
Xpackage body P is
Xfunction F return REAL is
X type T1 is (ONE,TWO,THREE,FOUR);
X subtype ST is T1 range ONE to THREE;
X variable V : ST;
Xbegin
X case ST'(ONE) is
X when ST'(ONE) => return 0.1;
X when ST'(ONE) to ST'(TWO) => return 9.0; -- ERROR : overlaps other choic
X end case; -- ERROR : part of subtype not represented
X end F;
Xend P ;
X
Xentity E is
X port (PT:inout REAL) ;
Xend E;
X
Xarchitecture BB of E is
X-- L_X_1: block
X begin
X process
X subtype ST is INTEGER range 20 to 45;
X variable V1 : ST := 20;
X begin
X case V1 is
X when 25 to 40 => return;
X when 20 to 25 => return; -- ERROR : overlaps other choice rang
X end case; -- ERROR : part of subtype not represented
X end process;
X-- end block;
Xend BB;
X
Xarchitecture AB of E is
X-- L_X_2: block
X begin
X process
X type T1 is (U,V,W,X,Y,Z);
X variable V1 : T1 := Z;
X begin
X case V1 is
X when U to Z => PT <= 0.9;
X when W to X => PT <= 1.1; -- ERROR : overlaps other choice rang
X end case;
X end process;
X-- end block;
Xend AB;
*-*-END-of-e-08-7-0-0004a.vhdl-*-*
echo x - e-08-7-0-0005a.vhdl
sed 's/^X//' >e-08-7-0-0005a.vhdl <<'*-*-END-of-e-08-7-0-0005a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-08-1-8-0005A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that a simple expression or a discrete range given as a choice in an
X-- alternative must be static.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xpackage P is
X function F (P1:NATURAL) return BOOLEAN ;
Xend P;
X
Xuse P.all ;
Xpackage body P is
X function F (P1:NATURAL) return BOOLEAN is
X subtype ST is CHARACTER range 'A' to 'Z';
X variable V : ST;
X begin
X V := ST'VAL(P1);
X case ST'PRED(V) is
X when 'A' to 'C' => return TRUE;
X when V to 'Z' => return FALSE; -- ERROR : non-static choic
X when ST'VAL(P1) to 'Z' => return FALSE; -- ERROR : non-static choic
X when others => return TRUE;
X end case;
X end F;
Xend P;
X
Xentity E is
X generic (G:INTEGER) ;
X port (PT:inout REAL) ;
X
Xend E;
X
Xarchitecture BB of E is
X-- L_X_1: block
X begin
X process
X variable V1 : static POSITIVE := 1;
X subtype ST is POSITIVE range 1 to 30;
X variable V2,V3 : ST := 1;
X begin
X case V3 * V2 is
X when V3 to 30 => return; -- ERROR : non-static choic
X when ST'(G) => return; -- ERROR : non-static choice
X when ST'(G) to 10 => return; -- ERROR : non-static choic
X when others => return;
X end case;
X end process;
X-- end block;
Xend BB;
X
Xarchitecture AB of E is
X-- L_X_2: block
X begin
X process
X subtype ST is INTEGER range G to -G;
X variable V : ST := 0;
X begin
X case - V is
X when ST range G to 0 => PT <= 0.9; -- ERROR : non-static choic
X when -1 to -G => PT <= 4.5; -- ERROR : non-static choic
X when others => PT <= 9.0;
X end case;
X end process;
X-- end block;
Xend AB;
*-*-END-of-e-08-7-0-0005a.vhdl-*-*
echo x - e-08-7-0-0006a.vhdl
sed 's/^X//' >e-08-7-0-0006a.vhdl <<'*-*-END-of-e-08-7-0-0006a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-08-1-8-0006A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the choice "others" is allowed only for the last alternative and
X-- as its only choice.
X-- DB 7.24.84
X-- DB 7/25/85
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xpackage P is
X function F return BOOLEAN ;
Xend P;
X
Xuse P.all ;
Xpackage body P is
X function F return BOOLEAN is
X type I1 is range 0 to 10;
X variable V1 : I1;
X begin
X case V1 is
X when others => return TRUE; -- ERROR : "others"not last alternative
X when 0 to 5 => return TRUE;
X when 6 to 10 => return FALSE;
X end case;
X end F;
Xend P;
X
Xuse P.all ;
Xpackage P is
X function F return REAL ;
Xend P ;
X
Xuse P.all ;
Xpackage body P is
Xfunction F return REAL is
X subtype ST is INTEGER range 5 downto -2;
X variable V1 : ST;
Xbegin
X case V1 is
X when 5 downto -1 => return 0.1;
X when -2 | others => return 9.0; -- ERROR : "others" not alone
X end case;
X end F;
Xend P ;
X
Xentity E is
X port (PT:inout REAL) ;
Xend E;
X
Xarchitecture BB of E is
X-- L_X_1:block
Xbegin
X process
X subtype ST is INTEGER range 20 to 45;
X variable V1 : ST := 20;
X begin
X case V1 is
X when 25 to 30 => return;
X when others => return; -- ERROR : "others" not last
X when 40 to 45 => return;
X end case;
X end process;
X-- end block;
Xend BB;
X
Xarchitecture AB of E is
X-- L_X_2:block
X type T1 is (U,V,W,X,Y,Z);
X signal S1 : T1;
Xbegin
X process
X begin
X S1 <= Z;
X case S1 is
X when V to Y => PT <= 0.9;
X when U | Z | others => PT <= 1.1; -- ERROR : "others" not alone
X end case;
X end process;
X-- end block;
Xend AB;
*-*-END-of-e-08-7-0-0006a.vhdl-*-*
echo x - e-08-7-0-0007a.vhdl
sed 's/^X//' >e-08-7-0-0007a.vhdl <<'*-*-END-of-e-08-7-0-0007a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-08-1-8-0007A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that an element simple name is not allowed as a choice of a case
X-- statement alternative.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
Xend E;
X
Xarchitecture BB of E is
X-- L_X_1: block
X type PH is record
X KEY : integer;
X NAME : Character;
X end record;
X type J is range 1 to 1000000000 ;
X begin
X process
X
X variable A_REC : PH;
X variable B,C,D,E : J := 2345;
X
X begin
X case B is
X when A_REC.KEY => C := D; -- ERROR AN ELEMENT SIMPLE NAME NOT ALLOWED IN CASE STATEMENT
X when C => null;
X when others => D := E;
X end case;
X end process;
X-- end block;
X end BB;
*-*-END-of-e-08-7-0-0007a.vhdl-*-*
echo x - e-08-7-0-0008a.vhdl
sed 's/^X//' >e-08-7-0-0008a.vhdl <<'*-*-END-of-e-08-7-0-0008a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-08-1-8-0008A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that non-discrete ranges are not allowed in case choices.
X-----------------------------------------------------------------------------
X-- In function P.F and body BB choice types do not match expression type.
X-- In function F and body AB the choice and expression types are non-discrete.
X-----------------------------------------------------------------------------
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xpackage P is
X function F return BOOLEAN ;
Xend P;
X
Xuse P.all ;
Xpackage body P is
X function F return BOOLEAN is
X type I1 is range 0 to 10;
X variable V1 : I1 := 6;
X type T1 is range 0.0 to 10.0;
X begin
X case V1 is
X when T1'(6.0) to T1'(10.0) => return FALSE; -- ERROR : non-discrete rang
X when others => return TRUE;
X end case;
X end F;
Xend P;
X
Xuse P.all ;
Xpackage P is
X function F return REAL ;
Xend P ;
X
Xuse P.all ;
Xpackage body P is
Xfunction F return REAL is
X subtype ST is INTEGER range 5 downto -2;
X subtype ST2 is REAL range 5.0 downto -2.0;
X variable V1 : ST2 := 2.4;
Xbegin
X case V1 is -- ERROR : non-discrete expression
X when ST2 range 5.0 to -1.0 => return 0.1; -- ERROR : non-discrete rang
X when others => return 9.0;
X end case;
X
X end F;
Xend P ;
X
Xentity E is
X port (PT:inout REAL) ;
Xend E;
X
Xarchitecture BB of E is
X-- L_X_1: block
X begin
X process
X subtype ST is INTEGER range 20 to 45;
X variable V1 : ST := 20;
X begin
X case V1 is
X when 20.0 to 22.0 => return; -- ERROR : non-discrete rang
X when others => return;
X end case;
X end process;
X-- end block;
Xend BB;
X
Xarchitecture AB of E is
X-- L_X_2: block
X begin
X process
X variable V1 : TIME := 1 Min;
X begin
X case V1 is -- ERROR : non-discrete expression
X when NS to US => PT <= 1.1; -- ERROR : non-discrete rang
X when others => PT <= 5.3;
X end case;
X end process;
X-- end block;
Xend AB;
*-*-END-of-e-08-7-0-0008a.vhdl-*-*
echo x - e-08-7-0-0009a.vhdl
sed 's/^X//' >e-08-7-0-0009a.vhdl <<'*-*-END-of-e-08-7-0-0009a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-08-1-8-0009A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the lower and upper bounds of a discrete range in case choices
X-- must be the same type.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xpackage P is
X function F (P1:NATURAL) return BOOLEAN ;
Xend P;
X
Xuse P.all ;
Xpackage body P is
X function F (P1:NATURAL) return BOOLEAN is
X subtype ST is CHARACTER range '0' to 'Z';
X variable V : ST;
X begin
X V := ST'VAL(P1);
X case ST'PRED(V) is
X when BIT ' ('1') to 'A' => return TRUE; -- ERROR:unmatched range bound
X when 'V' to 'Z' => return FALSE;
X when others => return TRUE;
X end case;
X end F;
Xend P;
X
Xentity E is
X generic (G:INTEGER) ;
X port (PT:inout REAL) ;
X
Xend E;
X
Xarchitecture BB of E is
X-- L_X_1: block
X begin
X process
X type T1 is range 1 to 30;
X subtype ST is INTEGER range 1 to 30;
X variable V2,V3 : ST := 1;
X begin
X case V3 * V2 is
X when T1'(20) to ST'(30) => return; -- ERROR : unmatched range bound
X when 10 => return;
X when others => return;
X end case;
X end process;
X-- end block;
Xend BB;
X
Xarchitecture AB of E is
X-- L_X_2: block
X begin
X process
X subtype ST is INTEGER range 10 downto -10;
X type ST2 is range 10 downto -10;
X variable V : ST := 0;
Xbegin
X case - V is
X when ST range 5 downto 0 => PT <= 0.9;
X when -1 downto ST2'(-5) => PT <= 4.5; -- ERROR : unmatched range bound
X when others => PT <= 9.0;
X end case;
X end process;
X-- end block;
Xend AB;
*-*-END-of-e-08-7-0-0009a.vhdl-*-*
echo x - e-08-7-0-0010a.vhdl
sed 's/^X//' >e-08-7-0-0010a.vhdl <<'*-*-END-of-e-08-7-0-0010a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-08-1-8-0010A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that static violations of range constraints (on case expression) are
X-- detected in lower and upper bounds in range specifications in case choices
X-- (discrete types, discrete types in arrays, discrete types in records).
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xpackage P is
X function F return BOOLEAN ;
Xend P;
X
Xuse P.all ;
Xpackage body P is
X function F return BOOLEAN is
X variable V1 : NATURAL := 6;
X begin
X case V1 is
X when -1 to 5 => return TRUE; -- ERROR : range violates constraint
X when -15 to -3 => return FALSE; -- ERROR : range violates constraint
X end case;
X end F;
Xend P;
X
Xuse P.all ;
Xpackage P is
X function F return REAL ;
Xend P ;
X
Xuse P.all ;
Xpackage body P is
Xfunction F return REAL is
X type T1 is (ONE,TWO,THREE,FOUR);
X subtype ST is T1 range ONE to THREE;
X variable V : ST;
Xbegin
X case V is
X when ONE => return 0.1;
X when TWO to FOUR => return 9.0; -- ERROR : range violates constraints
X end case;
X end F;
Xend P ;
X
Xentity E is
X port (PT:inout REAL) ;
Xend E;
X
Xarchitecture BB of E is
X-- L_X_1: block
X begin
X process
X subtype ST is INTEGER range 20 to 45;
X variable V1 : ST := 20;
X constant V2 : INTEGER := 14;
X begin
X case V1 is
X when 0 to 100 => return; -- ERROR : range violates constraint
X when V2 to 45 => return; -- ERROR : range violates constraint
X when others => return;
X end case;
X end process;
X-- end block;
Xend BB;
X
Xarchitecture AB of E is
X-- L_X_2: block
X signal V1 : CHARACTER range 'a' to 'z';
X begin
X process
X begin
X case V1 is
X when 'A' to 'Z' => PT <= 0.9; -- ERROR : range violates constraint
X when 'L' to 'c' => PT <= 1.1; -- ERROR : range violates constraint
X when others => PT <= 2.3;
X end case;
X end process;
X-- end block;
Xend AB;
*-*-END-of-e-08-7-0-0010a.vhdl-*-*
echo x - e-08-7-0-0011a.vhdl
sed 's/^X//' >e-08-7-0-0011a.vhdl <<'*-*-END-of-e-08-7-0-0011a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-08-1-8-0011A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that static violations of the case expression's range constraints are
X-- detected in case choices when choices are not ranges (discrete types,
X-- discrete types in arrays, discrete types in records).
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xpackage P is
X function F return BOOLEAN ;
Xend P;
X
Xuse P.all ;
Xpackage body P is
X function F return BOOLEAN is
X variable V1 : NATURAL := 9;
X begin
X case V1 is
X when 0 to 5 | -1 => return TRUE; -- ERROR:choice violates constraint
X when -15 => return FALSE; -- ERROR : choice violates constraints
X end case;
X end F;
Xend P;
X
Xuse P.all ;
Xpackage P is
X function F return REAL ;
Xend P ;
X
Xuse P.all ;
Xpackage body P is
Xfunction F return REAL is
X type T1 is (ONE,TWO,THREE,FOUR);
X subtype ST is T1 range ONE to THREE;
X variable V : ST;
Xbegin
X case V is
X when ONE | FOUR => return 0.1; -- ERROR : choice violates constraints
X when TWO to THREE => return 9.0;
X end case;
X end F;
Xend P ;
X
Xentity E is
X port (PT:inout REAL) ;
Xend E;
X
Xarchitecture BB of E is
X-- L_X_1: block
X begin
X process
X subtype ST is INTEGER range 20 to 45;
X variable V1 : ST := 20;
X constant V2 : INTEGER := 14;
X begin
X case V1 is
X when 20 | 10 | 30 => return; -- ERROR : choice violates constraints
X when V2 => return; -- ERROR : choice violates constraints
X when others => return;
X end case;
X end process;
X-- end block;
Xend BB;
X
Xarchitecture BB1 of E is
X-- L_X_2: block
X subtype BFALSE is BOOLEAN range FALSE to FALSE;
X begin
X process
X variable V1 : BFALSE;
X begin
X case V1 is
X when (BIT ' ('1') = BIT ' ('1')) => return;
X end case;
X end process;
X-- end block;
Xend BB1;
X
Xarchitecture AB of E is
X-- L_X_3: block
X signal V1 : CHARACTER range 'a' to 'z';
X begin
X process
X begin
X case V1 is
X when 'A' => PT <= 0.9; -- ERROR : choice violates constraints
X when 'L' => PT <= 1.1; -- ERROR : choice violates constraints
X when others => PT <= 2.3;
X end case;
X end process;
X-- end block;
Xend AB;
*-*-END-of-e-08-7-0-0011a.vhdl-*-*
echo x - e-08-7-0-0012a.vhdl
sed 's/^X//' >e-08-7-0-0012a.vhdl <<'*-*-END-of-e-08-7-0-0012a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-08-1-8-0012A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check static expression evaluation in lower and upper bounds in range
X-- specifications in case choices, all discrete types. Check by violating range
X-- constraint.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xpackage P is
X function F return BOOLEAN ;
Xend P;
X
Xuse P.all ;
Xpackage body P is
X function F return BOOLEAN is
X variable V1 : NATURAL := 7;
X constant V2 : INTEGER := 2;
X begin
X case V1 is
X when -1 to 5/3-9/2 => return TRUE; -- ERROR : range violatio
X when V2*(-9)+10 to -3 => return FALSE; -- ERROR : range violatio
X end case;
X end F;
Xend P;
X
Xentity E is
X port (PT:inout REAL) ;
Xend E;
X
Xarchitecture BB of E is
X-- L_X_1: block
X begin
X process
X subtype ST is INTEGER range 20 to 45;
X variable V1 : ST := 20;
X constant V2 : INTEGER := 14;
X begin
X case V1 is
X when 0*10+19 to 100/2-4 => return; -- ERROR : range violatio
X when V2+10/2 to 45 => return; -- ERROR : range violatio
X when others => return;
X end case;
X end process;
X-- end block;
Xend BB;
X
Xarchitecture AB of E is
X-- L_X_2: block
X type T1 is (ONE,TWO,THREE,FOUR);
X subtype ST is T1 range TWO to THREE;
X signal V : ST;
X begin
X process
X begin
X case V is
X when ONE to ST'PRED(THREE) => PT <= 0.9; -- ERROR : range violatio
X when THREE to ST'SUCC(THREE) => PT <= 2.3 ; -- ERROR : range violatio
X end case;
X end process;
X-- end block;
Xend AB;
*-*-END-of-e-08-7-0-0012a.vhdl-*-*
echo x - e-08-7-0-0013a.vhdl
sed 's/^X//' >e-08-7-0-0013a.vhdl <<'*-*-END-of-e-08-7-0-0013a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-08-1-8-0013A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that even when the context indicates that a case expression covers a
X-- smaller range of values than permitted by its type, an "others" alternative
X-- is required if the type value range is not fully covered by the set of
X-- choices.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xuse P.all ;
Xpackage P is
X function F return BIT ;
Xend P ;
X
Xuse P.all ;
Xpackage body P is
Xfunction F return BIT is
X type E is (W,X,Y,Z);
X variable V1 : E := X;
Xbegin
X while V1 <= Y loop
X case V1 is
X when W | X => return '0';
X when Y => return '1';
X end case; -- ERROR : "others" is still required
X end loop;
X end F;
Xend P ;
X
Xentity E is
X port (PT:BOOLEAN) ;
Xend E;
X
Xarchitecture AB of E is
X-- L_X_1: block
X begin
X process
X variable S : INTEGER := 0;
X begin
X if S > 10 and S < 20 then
X case S is
X when 10 to 15 => S := 5;
X when 16 to 19 => S := 10;
X end case; -- ERROR : "others" is still required
X end if;
X end process;
X-- end block;
Xend AB;
X
Xarchitecture BB of E is
X-- L_X_2: block
X begin
X process
X variable V : CHARACTER := 'L';
X begin
X if V = 'L' or V = 'M' or V = 'N' then
X case V is
X when 'L' | 'M' | 'N' => return;
X end case; -- ERROR : "others" is still required
X end if;
X end process;
X-- end block;
Xend BB;
*-*-END-of-e-08-7-0-0013a.vhdl-*-*
echo x - e-08-8-0-0001a.vhdl
sed 's/^X//' >e-08-8-0-0001a.vhdl <<'*-*-END-of-e-08-8-0-0001a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-08-1-9-0001A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that if a label appears at the end of a loop statement, it must
X-- repeat the label at the beginning of the loop statement.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
X port (PT:BOOLEAN) ;
Xend E;
X
Xarchitecture BB of E is
X-- L_X_1: block
X begin
X process
X begin
X L1: while 1/=1 loop
X return;
X end loop LL; -- ERROR : end loop label differs from loop label
X
X loop
X return;
X end loop L2; -- ERROR : end loop label without beginning loop label
X end process;
X-- end block;
Xend BB;
X
Xuse P.all ;
Xpackage P is
X function F return INTEGER ;
Xend P ;
X
Xuse P.all ;
Xpackage body P is
Xfunction F return INTEGER is
Xbegin
X for I in TRUE downto FALSE loop
X return 999;
X end loop L2; -- ERROR : end loop label without beginning loop label
X end F;
Xend P ;
*-*-END-of-e-08-8-0-0001a.vhdl-*-*
echo x - e-08-8-0-0002a.vhdl
sed 's/^X//' >e-08-8-0-0002a.vhdl <<'*-*-END-of-e-08-8-0-0002a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-08-1-9-0002A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that a loop parameter is not allowed on the left-hand side of an
X-- assignment statement.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
X port (PT:BOOLEAN) ;
Xend E;
X
Xarchitecture BB of E is
X-- L_X_1: block
X begin
X process
X begin
X for I in 96 to 100 loop
X I := I - 1; -- ERROR : attempted assignment to loop parameter
X return;
X end loop;
X end process;
X-- end block;
Xend BB;
X
Xuse P.all ;
Xpackage P is
X function F return INTEGER ;
Xend P ;
X
Xuse P.all ;
Xpackage body P is
Xfunction F return INTEGER is
Xbegin
X for I in TRUE downto FALSE loop
X I := TRUE; -- ERROR : attempted assignment to loop parameter
X return 999;
X end loop;
X end F;
Xend P ;
*-*-END-of-e-08-8-0-0002a.vhdl-*-*
echo x - e-08-8-0-0003a.vhdl
sed 's/^X//' >e-08-8-0-0003a.vhdl <<'*-*-END-of-e-08-8-0-0003a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-08-1-9-0003A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that a condition in an iteration scheme (while) must be of a boolean
X-- type.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xuse P.all ;
Xpackage P is
X function F return REAL ;
Xend P ;
X
Xuse P.all ;
Xpackage body P is
Xfunction F return REAL is
X variable V : REAL;
Xbegin
X while not '0' loop -- ERROR : while_condition not boolean expression
X return V;
X end loop;
X while 23 mod (5) loop -- ERROR : while_condition not boolean expression
X return 3.5;
X end loop;
X while abs V loop -- ERROR : while_condition not boolean expression
X return -5.964;
X end loop;
X end F;
Xend P ;
X
Xuse P.all ;
Xpackage P is
X function F return REAL ;
Xend P ;
X
Xuse P.all ;
Xpackage body P is
Xfunction F return REAL is
X variable V : REAL;
Xbegin
X return 3.5;
X end F;
Xend P ;
X
X-- with function F;
Xuse P.F ;
Xentity E is
X port (PT:BOOLEAN) ;
Xend E;
X
Xarchitecture BB of E is
X-- L_X_1: block
X begin
X process
X begin
X while '1' and '0' loop -- ERROR : while_condition not boolean expression
X return;
X end loop;
X while NS * MIN loop -- ERROR : while_condition not boolean expression
X return;
X end loop;
X while F loop -- ERROR : while_condition not boolean expression
X return;
X end loop;
X while "HELL" & "O" loop -- ERROR : while_condition not boolean expression
X return;
X end loop;
X end process;
X-- end block;
Xend BB;
*-*-END-of-e-08-8-0-0003a.vhdl-*-*
echo x - e-08-8-0-0004a.vhdl
sed 's/^X//' >e-08-8-0-0004a.vhdl <<'*-*-END-of-e-08-8-0-0004a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-08-1-9-0004A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that a loop parameter is an object whose type is the base type
X-- of the discrete range (check using an equality operation with an
X-- operand of incompatible type).
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xuse P.all ;
Xpackage P is
X function F return REAL ;
Xend P ;
X
Xuse P.all ;
Xpackage body P is
Xfunction F return REAL is
X type E is (A,B,C,D);
X type E1 is (A,B,C);
X type T is range 11 to 15;
X variable V : T;
Xbegin
X for I in D downto A loop
X exit when I = E1 ' (C); -- ERROR : types do not match
X end loop;
X for I in BIT ' ('1') to '0' loop
X exit when I = CHARACTER ' ('0'); -- ERROR : types do not match
X end loop;
X for I in '~' downto 'z' loop
X exit when I = BIT ' ('1'); -- ERROR : types do not match
X end loop;
XL1: for I in -10 to 10 loop
X exit when I = V; -- ERROR : types do not match
X end loop L1;
X return 0.0003;
X end F;
Xend P ;
X
Xentity E is
X port (PT:BOOLEAN) ;
Xend E;
X
Xarchitecture BB of E is
X-- L_X_1: block
X begin
X process
X type E1 is (X,Y,Z);
X type T is range 2 downto -5;
X variable V : NATURAL;
X variable V2 : T;
X begin
XL2: for I in V2 to 9 * V2 loop
X exit when I = '0'; -- ERROR : types do not match
X end loop L2;
X for I in 'Z' downto 'A' loop
X exit when I = Z; -- ERROR : types do not match
X end loop;
X for I in FALSE to TRUE loop
X exit when I = 'T'; -- ERROR : types do not match
X end loop;
XL3: for I in 10 downto V loop
X exit when I = -7.0; -- ERROR : types do not match
X end loop L3;
X for I in 2 to 5 loop
X exit when I = 2.0; -- ERROR : types do not match
X end loop;
X end process;
X-- end block;
Xend BB;
*-*-END-of-e-08-8-0-0004a.vhdl-*-*
echo x - e-08-8-0-0005a.vhdl
sed 's/^X//' >e-08-8-0-0005a.vhdl <<'*-*-END-of-e-08-8-0-0005a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-08-1-9-0005A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the discrete range of a loop parameter specification must
X-- have discrete upper and lower bounds.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
X
X
Xuse P.all ;
Xpackage P is
X function F return REAL ;
Xend P ;
X
Xuse P.all ;
Xpackage body P is
Xfunction F return REAL is
Xbegin
X for I in 1.9 downto -2.3 loop -- ERROR : non-discrete loop parameter
X return 3.5;
X end loop;
X for I in 23 / 6 to 5.9 loop -- ERROR : non-discrete loop parameter
X return 3.5;
X end loop;
X end F;
Xend P ;
X
Xentity E is
X port (PT:BOOLEAN) ;
Xend E;
X
Xarchitecture BB of E is
X-- L_X_1: block
X begin
X process
X begin
X for I in PS downto FS loop -- ERROR : non-discrete loop parameter
X return;
X end loop;
X for I in FS / PS to FS loop -- ERROR : non-discrete loop parameter
X return;
X end loop;
X end process;
X-- end block;
Xend BB;
*-*-END-of-e-08-8-0-0005a.vhdl-*-*
echo x - e-08-8-0-0006a.vhdl
sed 's/^X//' >e-08-8-0-0006a.vhdl <<'*-*-END-of-e-08-8-0-0006a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-08-1-9-0006A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the scope of the loop parameter is limited to the loop statement
X-- (that is, a reference to it outside the loop statement is illegal).
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xuse P.all ;
Xpackage P is
X function F return REAL ;
Xend P ;
X
Xuse P.all ;
Xpackage body P is
Xfunction F return REAL is
X variable V : INTEGER;
Xbegin
X while I < 23 loop -- ERROR : reference to I outside its scope
X for I in 1 to 23 loop
X return 3.5;
X end loop;
X V := I + 1; -- ERROR : reference to I outside its scope
X I := V; -- ERROR : reference to I outside its scope
X end loop;
X return I ; -- ERROR : reference to I outside its scope
X end F;
Xend P ;
X
Xentity E is
X port (PT:BOOLEAN) ;
Xend E;
X
Xarchitecture BB of E is
X-- L_X_1: block
X begin
X process
X variable V : REAL;
X begin
X V := I; -- ERROR : reference to I outside its scope
X if I = 'C' then -- ERROR : reference to I outside its scope
X return;
X else
X for I in 'Z' downto 'A' loop
X return;
X end loop;
X case I is -- ERROR : reference to I outside its scope
X when 'A' => return;
X when others => null;
X end case;
X end if;
X end process;
X-- end block;
Xend BB;
*-*-END-of-e-08-8-0-0006a.vhdl-*-*
echo x - e-08-8-0-0007a.vhdl
sed 's/^X//' >e-08-8-0-0007a.vhdl <<'*-*-END-of-e-08-8-0-0007a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-08-1-9-0007A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the upper and lower bounds of the discrete range of a loop
X-- parameter specification must be the same type.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
X
Xuse P.all ;
Xpackage P is
X function F return REAL ;
Xend P ;
X
Xuse P.all ;
Xpackage body P is
Xfunction F return REAL is
X type LETTER is (A,B,C,D);
X type NUMBER is (ONE,TWO,THREE,FOUR);
X type T is range 11 to 15;
X variable V : T;
Xbegin
X for I in D downto ONE loop
X null; -- ERROR : loop parameter types do not match
X end loop;
X for I in 1 to FOUR loop
X null; -- ERROR : loop parameter types do not match
X end loop;
X for I in '0' to T loop
X null; -- ERROR : loop parameter types do not match
X end loop;
XL1: for I in ONE to '1' loop
X null; -- ERROR : loop parameter types do not match
X end loop L1;
X return 0.0003;
X end F;
Xend P ;
*-*-END-of-e-08-8-0-0007a.vhdl-*-*
echo x - e-08-9-0-0001a.vhdl
sed 's/^X//' >e-08-9-0-0001a.vhdl <<'*-*-END-of-e-08-9-0-0001a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-08-1-A-0001A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that a next statement with a loop label is only allowed within
X-- the labeled loop.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
X port (PT:BOOLEAN) ;
Xend E;
X
Xarchitecture BB of E is
X-- L_X_1: block
X begin
X process
X variable V1 : INTEGER;
X begin
X L1: loop
X V1 := 1;
X loop
X V1 := 4;
X end loop;
X end loop L1;
X next L1; -- ERROR : labelled next outside named loop
X L2: loop
X V1 := -93;
X end loop L2;
X L3: loop
X V1 := V1 + 3;
X next L1; -- ERROR : labelled next inside non-matching loop
X end loop L3;
X return;
X end process;
X-- end block;
Xend BB;
X
Xuse P.all ;
Xpackage P is
X function F return BOOLEAN ;
Xend P ;
X
Xuse P.all ;
Xpackage body P is
Xfunction F return BOOLEAN is
X variable V1 : INTEGER;
Xbegin
X loop
X V1 := 1;
X L1: loop
X V1 := -1;
X end loop L1;
X next L1; -- ERROR : labelled next outside matching loop
X end loop;
X return FALSE;
X end F;
Xend P ;
*-*-END-of-e-08-9-0-0001a.vhdl-*-*
echo x - e-08-9-0-0002a.vhdl
sed 's/^X//' >e-08-9-0-0002a.vhdl <<'*-*-END-of-e-08-9-0-0002a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-08-1-A-0002A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that a next statement without a loop label is allowed only within a
X-- labeled or unlabeled loop.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
X port (PT:BOOLEAN) ;
Xend E;
X
Xarchitecture BB of E is
X-- L_X_1: block
X begin
X process
X variable V1 : INTEGER;
X begin
X L1: loop
X V1 := 1;
X end loop L1;
X next; -- ERROR : next statement outside a loop
X return;
X end process;
X-- end block;
Xend BB;
X
Xuse P.all ;
Xpackage P is
X function F return BOOLEAN ;
Xend P ;
X
Xuse P.all ;
Xpackage body P is
Xfunction F return BOOLEAN is
Xbegin
X next; -- ERROR : next statement outside a loop
X return FALSE;
X end F;
Xend P ;
*-*-END-of-e-08-9-0-0002a.vhdl-*-*
echo x - e-08-9-0-0003a.vhdl
sed 's/^X//' >e-08-9-0-0003a.vhdl <<'*-*-END-of-e-08-9-0-0003a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-08-1-A-0003A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the condition in a next statement must be of a boolean type.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
X port (PT:BOOLEAN) ;
Xend E;
X
Xarchitecture BB of E is
X-- L_X_1: block
X begin
X process
X variable V1 : INTEGER;
X begin
X L1: loop
X V1 := 1;
X loop
X V1 := 4;
X next L1 when 3.5; -- ERROR : non-Boolean condition
X end loop;
X exit when 'A'; -- ERROR : non-Boolean condition
X end loop L1;
X L2: loop
X V1 := V1 + 3;
X next when 387; -- ERROR : non-Boolean condition
X end loop L2;
X return;
X end process;
X-- end block;
Xend BB;
X
Xuse P.all ;
Xpackage P is
X function F return BOOLEAN ;
Xend P ;
X
Xuse P.all ;
Xpackage body P is
Xfunction F return BOOLEAN is
X variable V1 : INTEGER;
Xbegin
X loop
X V1 := 1;
X L1: loop
X V1 := -1;
X exit L1 when V1; -- ERROR : non-Boolean condition
X end loop L1;
X end loop;
X return FALSE;
X end F;
Xend P ;
*-*-END-of-e-08-9-0-0003a.vhdl-*-*
echo x - s-08-0-0-0001a.vhdl
sed 's/^X//' >s-08-0-0-0001a.vhdl <<'*-*-END-of-s-08-0-0-0001a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-08-1-0-0001A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that all sequential statements are permitted in a sequence of
X-- statements.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E1 is
X port (A:in BIT; B:in BIT; C:out BIT) ;
Xend E1;
X
Xarchitecture B1 of E1 is
X-- L_X_1: block
X signal S1,S2: BIT ;
X begin
X process ( S1,S2 )
X variable V1:INTEGER:=0;
X
X begin
X if A=B then
X C<='0' after 2 ns;
X elsif A='0' then
X C<='0' after 3 ns;
X else
X C<='0' after 4 ns;
X end if;
X
X case B is
X when '0' =>
X V1:=1;
X when '1' =>
X V1:=2;
X end case;
X
X LP: while V1>0 loop
X V1:=V1-1;
X end loop;
X
X LP1: for I in 1 to 2 loop
X V1:=V1+1;
X end loop;
X
X LP2: for I in 2 downto 1 loop
X V1:=V1-1;
X end loop;
X
X LP3: for I in 1 to 10 loop
X V1:=V1+1;
X next LP3 when V1=3;
X exit LP3 when V1=7;
X end loop;
X
X-- enable S1,S2; -- 7.2
X wait on S1, S2 ; -- 1076
X-- disable S2; -- 7.2
X-- (there is no 1076 equivalent to the above 7.2 disable stmt.)
X Null;
X return;
X end process ;
X-- end block L_X_1 ;
Xend B1;
*-*-END-of-s-08-0-0-0001a.vhdl-*-*
echo x - s-08-0-0-0001b.vhdl
sed 's/^X//' >s-08-0-0-0001b.vhdl <<'*-*-END-of-s-08-0-0-0001b.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-08-1-0-0001B.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that an empty sequence of statements is permitted (in process
X-- statements, subprogram declarations, if statements, case statements,
X-- and loop statements).
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
X port (PT: BOOLEAN) ;
Xend E;
X
Xuse P1.all ;
Xpackage body P1 is
Xfunction F return BOOLEAN ;
Xprocedure P ;
Xend P1 ;
X
Xuse P1.all ;
Xpackage body P1 is
X
Xfunction F return BOOLEAN is
Xbegin
Xend F;
X -- Sequence of statments in a function body
X -- can be null.
X
Xprocedure P is
Xbegin
Xend P;
X -- Sequence of statments in a procedure body
X -- can be null.
Xend P1 ;
X
Xarchitecture BB1 of E is
X-- L_X_1: block
X begin
X process
X begin
X if FALSE = FALSE then
X end if;
X -- Sequence of statements in the then
X -- clause of an if statement can be null.
X
X if FALSE = FALSE then
X return;
X else
X end if;
X -- Sequence of statements in the else
X -- clause of an if statement can be null.
X
X for LP in FALSE to TRUE loop
X end loop;
X -- Sequence of statments in a loop statement
X -- can be null.
X
X case TRUE is
X when TRUE => ;
X when FALSE => ;
X end case;
X -- Sequence of statements in a case statement
X -- alternative can be null.
X
X return;
X end process;
X-- end block;
Xend BB1;
X
Xarchitecture BB2 of E iS
X-- L_X_1: block
X begin
X process
X begin
X end process; -- Sequence of statements in a process
X -- statement can be null.
X-- end block;
Xend BB2;
*-*-END-of-s-08-0-0-0001b.vhdl-*-*
echo x - s-08-1-0-0001a.vhdl
sed 's/^X//' >s-08-1-0-0001a.vhdl <<'*-*-END-of-s-08-1-0-0001a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-08-1-1-0001A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that each signal name in the signal name list of an WAIT
X-- statement may be any signal including the implicitly
X-- declared signal GUARDS and attributes that are signals.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity W is
X port (PT : in boolean) ;
Xend W;
X
X
Xarchitecture AB of W is
X-- L_X_1: block
X signal S1,S2 : integer;
X begin
X process (S1,S2,GUARD)
X begin
X-- enable S1,S2,GUARD; -- 72.
X wait on S1,S2,GUARD; -- 1076
X end process;
X-- end block;
Xend AB;
*-*-END-of-s-08-1-0-0001a.vhdl-*-*
echo x - s-08-10-00001a.vhdl
sed 's/^X//' >s-08-10-00001a.vhdl <<'*-*-END-of-s-08-10-00001a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-08-1-B-0001A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the when clause is optional.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
Xend E;
X
Xarchitecture AB of E is
X-- L_X_1: block
X begin
X process
X variable V1 :integer ;
X variable B1 : boolean := true ;
X begin
X L1 : loop
X V1 := 1;
X next L1;
X end Loop L1;
X end process;
X-- end block;
Xend AB;
X
*-*-END-of-s-08-10-00001a.vhdl-*-*
echo x - s-08-10-00002a.vhdl
sed 's/^X//' >s-08-10-00002a.vhdl <<'*-*-END-of-s-08-10-00002a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-08-1-B-0002A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the loop label is optional.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
Xend E;
X
Xarchitecture AB of E is
X-- L_X_1: block
X begin
X process
X variable V1, V2 : integer;
X variable B1 : boolean := true;
X begin
X loop
X V2 := V1 - V2;
X exit when B1;
X end loop;
X end process;
X-- end block;
X end AB;
*-*-END-of-s-08-10-00002a.vhdl-*-*
echo x - s-08-11-00001a.vhdl
sed 's/^X//' >s-08-11-00001a.vhdl <<'*-*-END-of-s-08-11-00001a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-08-1-C-0001A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that there may be multiple return statements in a function body.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xpackage P is
X function F return BIT ;
Xend P;
X
Xuse P.all ;
Xpackage body P is
X function F return BIT is
X begin
X return '0';
X return '1';
X end F;
Xend P;
X
Xuse P.all ;
Xpackage P is
X function F return TIME ;
Xend P ;
X
Xuse P.all ;
Xpackage body P is
Xfunction F return TIME is
Xbegin
X return 500 PS;
X return 33 US;
X return 19 S;
X return 1 MIN;
X end F;
Xend P ;
*-*-END-of-s-08-11-00001a.vhdl-*-*
echo x - s-08-11-00002a.vhdl
sed 's/^X//' >s-08-11-00002a.vhdl <<'*-*-END-of-s-08-11-00002a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-08-1-C-0002A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that there may be multiple return statements in a procedure body
X-- or in a process statement.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
X port (P:BOOLEAN) ;
Xend E;
X
Xarchitecture BB of E is
X-- L_X_1: block
X begin
X process
X begin
X return;
X return;
X return;
X return;
X end process;
X-- end block;
Xend BB;
X
Xuse P.all ;
Xpackage P is
Xprocedure P1 ;
Xend P ;
X
Xuse P.all ;
Xpackage body P is
Xprocedure P1 is
X begin
X return;
X return;
Xend ;
Xend P ;
*-*-END-of-s-08-11-00002a.vhdl-*-*
echo x - s-08-11-00003a.vhdl
sed 's/^X//' >s-08-11-00003a.vhdl <<'*-*-END-of-s-08-11-00003a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-08-1-C-0003A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that there may be a return statement within a compound statement.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xpackage P is
X function F return BIT ;
Xend P;
X
Xuse P.all ;
Xpackage body P is
X function F return BIT is
X variable RESULT : BIT := '1';
X begin
X if TRUE then
X return result;
X else
X result := '0';
X return result;
X end if;
X end F;
Xend P;
X
Xentity E is
X port (PT:BOOLEAN) ;
Xend E;
X
Xarchitecture BB of E is
X-- L_X_1: block
X begin
X process
X begin
X loop
X return;
X end loop;
X end process;
X-- end block;
Xend BB;
X
Xuse P.all ;
Xpackage P is
X function F(X:NATURAL) return TIME ;
Xend P ;
X
Xuse P.all ;
Xpackage body P is
Xfunction F(X:NATURAL) return TIME is
Xbegin
X case X is
X when 0 to 100 => return 1FS;
X when others => return 1US;
X end case;
X return 1S;
Xend F;
Xend P ;
*-*-END-of-s-08-11-00003a.vhdl-*-*
echo x - s-08-11-00004a.vhdl
sed 's/^X//' >s-08-11-00004a.vhdl <<'*-*-END-of-s-08-11-00004a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-08-1-C-0004A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that in a function the subtype of the return expression and the
X-- subtype denoted by the type mark occurring after the word "return"
X-- may be different provided both their base types and the number od components
X-- are the same; check for full arrays, slices, aggregates; that is,
X-- detection of constraint error is by th analyzer.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xpackage P1 is
X type E is (A,B,C,D);
X subtype E1 is E range C to D;
X subtype E2 is E range A to B;
X type PH is range 1 to 24
X units
X U;
X X=3U;
X Y=2X;
X end units;
X subtype PH1 is PH range X to Y;
X type AR1 is array (POSITIVE range <>) of PH;
X type AR2 is array (0 to 7) of BIT;
X type AR4 is array (POSITIVE range <>) of BIT;
Xend P1;
X
X-- with package P1;
Xuse P1.all;
Xpackage P2 is
X function F return E ;
X function G return E1 ;
X function H return E2 ;
X function J return PH1 ;
X function K return AR1 ;
X function M return AR1 ;
X function N return AR4 ;
Xend P2;
X
Xuse P2.all ;
Xpackage body P2 is
X function F return E is
X variable V : E1 := C;
X begin
X return V;
X end F;
X function G return E1 is
X begin
X return D;
X end G;
X function H return E2 is
X variable V : E := C;
X begin
X return V;
X end H;
X function J return PH1 is
X begin
X return X;
X end J;
X function K return AR1 is
X variable V : AR1(49 to 50) ;
X begin
X V := (5U,X) ;
X return V;
X end K;
X function M return AR1 is
X subtype AR3 is AR1(2 to 3);
X variable V : AR3 ;
X begin
X V := (U, 24U) ;
X return V;
X end M;
X function N return AR4 is
X variable V : AR4(1 to 7) ;
X begin
X V := ('0',others=>'1');
X return V(1 to 3);
X end N;
Xend P2;
X
X-- with package P1;
Xuse P1.all;
Xpackage P1 is
X function F return E1 ;
Xend P1 ;
X
Xuse P1.all;
Xpackage body P1 is
Xfunction F return E1 is
X variable V : E1 := C;
Xbegin
X return V;
X end F;
Xend P1 ;
X
X-- with package P1;
Xuse P1.all;
Xpackage P1 is
Xfunction G return E2 ;
Xend P1 ;
X
Xpackage body P1 is
Xfunction G return E2 is
Xbegin
X return A;
Xend G;
Xend P1 ;
X
X-- with package P1;
Xuse P1.all;
Xpackage P1 is
Xfunction H return PH ;
Xend P1 ;
X
Xuse P1.all ;
Xpackage body P1 is
Xfunction H return PH is
X variable V : PH1 := 4U;
Xbegin
X return V;
Xend H;
Xend P1 ;
X
X-- with package P1;
Xuse P1.all;
Xpackage P1 is
Xfunction J return AR1 ;
Xend P1 ;
X
Xuse P1.all;
Xpackage body P1 is
Xfunction J return AR1 is
Xbegin
X return (1=>10U,2=>2Y);
Xend J;
Xend P1 ;
X
X-- with package P1;
Xuse P1.all;
Xpackage P1 is
Xfunction K return AR2 ;
Xend P1 ;
X
Xuse P1.all;
Xpackage body P1 is
Xfunction K return AR2 is
Xbegin
X return (4|5=>'1',others=>'0');
Xend K;
Xend P1 ;
X
Xuse P1.all ;
Xpackage P1 is
Xfunction L return BIT_VECTOR ;
Xend P1 ;
X
Xuse P1.all ;
Xpackage body P1 is
Xfunction L return BIT_VECTOR is
Xbegin
X return O"074";
Xend L;
Xend P1 ;
X
*-*-END-of-s-08-11-00004a.vhdl-*-*
echo x - s-08-11-00005a.vhdl
sed 's/^X//' >s-08-11-00005a.vhdl <<'*-*-END-of-s-08-11-00005a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-08-1-C-0005A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that a return statement is not required in a process statement
X-- or in a procedure body.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity e is
Xend E;
X
Xarchitecture AB of E is
X-- L_X_1: block
X begin
X process
X begin
X null;
X end process;
X-- end block;
Xend AB;
X
Xuse P1.all ;
Xpackage P1 is
Xprocedure P ;
Xend P1 ;
X
Xuse P1.all ;
Xpackage body P1 is
Xprocedure P is
X begin
X null;
Xend;
Xend P1 ;
*-*-END-of-s-08-11-00005a.vhdl-*-*
echo x - s-08-12-00001a.vhdl
sed 's/^X//' >s-08-12-00001a.vhdl <<'*-*-END-of-s-08-12-00001a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-08-1-D-0001A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that a null statement is permitted in any sequence of statements.
X-- Check in subprogram bodies and in process, if case, and loop statements.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
X
Xuse P.all ;
Xpackage P is
X function f return boolean ;
Xend P ;
X
Xuse P.all ;
Xpackage body P is
Xfunction f return boolean is
X begin
X null;
X return true;
X end f;
Xend P ;
X
Xentity E is
Xend E;
X
Xarchitecture AB of E is
X-- L_X_1: block
X begin
X process
X variable I : Boolean ;
X begin
X if TRUE then
X null;
X elsif false then
X null;
X else
X null;
X end if;
X
X case I is
X when false => null;
X when true => null;
X end case;
X
X loop
X null;
X end loop;
X end process;
X-- end block;
Xend AB;
X
X
X
*-*-END-of-s-08-12-00001a.vhdl-*-*
echo x - s-08-2-0-0001a.vhdl
sed 's/^X//' >s-08-2-0-0001a.vhdl <<'*-*-END-of-s-08-2-0-0001a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-08-1-3-0001A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the severity clause is optional.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity AL is
X port ( A : inout Boolean;
X B : inout Boolean) ;
X end AL;
Xarchitecture AAL of AL is
X
X begin
X assert ( A and B)
X report " signals both high " ;
Xend AAL ;
X
X
*-*-END-of-s-08-2-0-0001a.vhdl-*-*
echo x - s-08-2-0-0002a.vhdl
sed 's/^X//' >s-08-2-0-0002a.vhdl <<'*-*-END-of-s-08-2-0-0002a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-08-1-3-0002A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the report clause is optional.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity AL is
X port ( A : in boolean) ;
Xend AL ;
X
Xarchitecture AAL of AL is
Xbegin
X assert ( not A)
X severity WARNING;
Xend AAL;
*-*-END-of-s-08-2-0-0002a.vhdl-*-*
echo x - s-08-3-0-0001a.vhdl
sed 's/^X//' >s-08-3-0-0001a.vhdl <<'*-*-END-of-s-08-3-0-0001a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-08-1-4-0001A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that there may be multiple signal names (separated by commas) on the
X-- left-hand side (with either a single waveform element or multiple waveform
X-- elements on the right-hand side).
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
X
Xentity ENT_1 is
X port (X,Y: inout BIT; S: inout BIT_VECTOR; COUT: out BIT) ;
Xend ENT_1;
X
Xarchitecture BB_1 of ENT_1 is
X-- L_X_1: block
X
X component COMP_1
X generic (P_1 : TIME);
X port (A: in BIT; SOUT: out BIT) ;
X end component ;
X signal S1, S2:BIT ;
X signal S3: BIT_VECTOR (1 to 10) ;
X signal S4, S5, S6: BIT;
X
X begin
X process
X variable V1: BIT;
Xbegin
X ( X, Y, S(3) ) <= V1;
X ( X, Y ) <= V1 after 2 ns;
X ( Y, S(1) ) <= V1 after 2 ns, '1' after 4 ns, '0' after 6 ns;
X ( X, S(5) ) <= S1;
X ( S1, S2 ) <= S1 after 5 ns;
X ( S3(5), S4 ) <= S1 after 5 ns, '0' after 15 ns;
X end process;
X-- end block;
Xend BB_1;
*-*-END-of-s-08-3-0-0001a.vhdl-*-*
echo x - s-08-3-0-0002a.vhdl
sed 's/^X//' >s-08-3-0-0002a.vhdl <<'*-*-END-of-s-08-3-0-0002a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-08-1-4-0002A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that there may be multiple waveform elements (separated by commas) on
X-- the right-hand side (with either a single signal or multiple signals on the
X-- left-hand side).
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
X
X
Xentity ENT_1 is
X port (X,Y: inout BIT; S: inout BIT_VECTOR; COUT: out BIT) ;
Xend ENT_1;
X
X
Xarchitecture AB_1 of ENT_1 is
X-- L_X_1: block
X component COMP_1
X generic (P_1 : TIME);
X port (A: in BIT; SOUT: out BIT) ;
X end component ;
X signal S1, S2:BIT ;
X signal S3: BIT_VECTOR (1 to 10) ;
X signal S4, S5, S6: BIT;
X begin
X process
X variable V1: BIT;
X begin
X ( X, Y ) <= V1, '1' after 2 ns;
X ( X, Y, S(3) ) <= V1 after 2 ns;
X Y <= V1 after 2 ns, '1' after 4 ns, '0' after 6 ns;
X ( X, S(5) ) <= S1;
X ( S1, S2, S6 ) <= S1 after 5 ns, '1' after 15 ns;
X S3(5) <= S1 after 5 ns, '0' after 15 ns, '1' after 30 ns;
X end process;
X-- end block;
Xend AB_1;
*-*-END-of-s-08-3-0-0002a.vhdl-*-*
echo x - s-08-3-0-0003a.vhdl
sed 's/^X//' >s-08-3-0-0003a.vhdl <<'*-*-END-of-s-08-3-0-0003a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-08-1-4-0003A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that a time expression may have a static value of zero.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
X
Xentity ENT_1 is
X port (X,Y: in BIT; COUT: out BIT) ;
Xend ENT_1;
X
X
Xarchitecture AB_1 of ENT_1 is
X-- L_X_1: block
X component COMP_1
X generic (P_1 : TIME);
X port (A: in BIT; SOUT: out BIT) ;
X end component ;
X signal S1:BIT ;
X signal SOUT : BIT ;
X begin
X process
X variable V1: BIT;
X begin
X SOUT <= S1 after 0 ns;
X COUT <= V1 after 0 ns;
X return;
X end process;
X-- end block;
Xend AB_1;
*-*-END-of-s-08-3-0-0003a.vhdl-*-*
echo x - s-08-3-0-0004a.vhdl
sed 's/^X//' >s-08-3-0-0004a.vhdl <<'*-*-END-of-s-08-3-0-0004a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-08-1-4-0004A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the "after" plus time expression portion of a waveform element is
X-- optional.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity ENT_1 is
X port (X,Y: in BIT; COUT: out BIT) ;
Xend ENT_1;
X
Xarchitecture AB_1 of ENT_1 is
X-- L_X_1: block
X component COMP_1
X generic (P_1 : TIME);
X port (A: in BIT; SOUT: out BIT) ;
X end component ;
X signal S1:BIT ;
X signal SOUT : BIT ;
X begin
X process
X variable V1: BIT :='1';
X begin
X COUT <= V1;
X SOUT <= S1;
X return;
X end process;
X-- end block;
Xend AB_1;
*-*-END-of-s-08-3-0-0004a.vhdl-*-*
echo x - s-08-3-0-0005a.vhdl
sed 's/^X//' >s-08-3-0-0005a.vhdl <<'*-*-END-of-s-08-3-0-0005a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-08-1-4-0005A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the signal name on the left-hand side may be a simple name, an
X-- indexed name, a slice name, a selected name.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity ENT_1 is
X port (X,Y: in BIT; S: out BIT; COUT: out BIT_VECTOR) ;
Xend ENT_1;
X
Xarchitecture AB_1 of ENT_1 is
X-- L_X_1: block
X type UA is array (NATURAL range <>) of BIT ;
X subtype ARAY_1 is UA (0 to 500) ;
X subtype ARAY_2 is UA (1 to 10);
X type REC_1 is record
X RE_1: BIT;
X RE_2: INTEGER;
X end record;
X signal S1: BIT;
X signal S2: BIT ;
X signal S3: REC_1;
X signal S4: ARAY_2;
X signal S5: ARAY_1;
X begin
X process
X begin
X S1 <= S2;
X S3.RE_1 <= S2;
X S5(200) <= S2 or S1;
X S4(1 to 5) <= S5(21 to 25);
X return;
X end process;
X-- end block;
Xend AB_1;
*-*-END-of-s-08-3-0-0005a.vhdl-*-*
echo x - s-08-3-0-0006a.vhdl
sed 's/^X//' >s-08-3-0-0006a.vhdl <<'*-*-END-of-s-08-3-0-0006a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-08-1-4-0006A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that implicit type conversion is performed when the right-hand
X-- side value expression is of type universal integer or universal real.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
Xend E;
X
Xarchitecture AB of E is
X-- BB:block
X type NEW_INT is range -300 to 300;
X type NEW_REAL is range -300.0 to 300.0;
X signal S1 : INTEGER;
X signal S2 : REAL;
X signal S3 : NEW_INT;
X signal S4 : NEW_REAL;
X signal S5 : INTEGER range 3 to 80;
X signal S6 : NEW_REAL range 3.0 to 80.0;
X begin
X S1 <= 4;
X -- implicit type conversion from universal integer or universal real.
X S2 <= 20.9;
X -- implicit type conversion from universal integer or universal real.
X S3 <= 299;
X -- implicit type conversion from universal integer or universal real.
X S4 <= -299.0;
X -- implicit type conversion from universal integer or universal real.
X S5 <= 79;
X -- implicit type conversion from universal integer or universal real.
X S6 <= 79.99;
X -- implicit type conversion from universal integer or universal real.
X-- end block;
Xend AB;
*-*-END-of-s-08-3-0-0006a.vhdl-*-*
echo x - s-08-4-0-0001a.vhdl
sed 's/^X//' >s-08-4-0-0001a.vhdl <<'*-*-END-of-s-08-4-0-0001a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-08-1-5-0001A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the variable name on the left-hand side may be a simple name, an
X-- indexed name, a slice name, a selected name.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity ENT_1 is
X port (X,Y: in BIT; COUT: out BIT) ;
Xend ENT_1;
X
Xarchitecture BB_1 of ENT_1 is
X-- L_X_1: block
X begin
X process
X type UA is array (NATURAL range <>) of BIT ;
X subtype ARAY_1 is UA (0 to 500) ;
X subtype ARAY_2 is UA (1 to 10);
X type REC_1 is record
X RE_1: BIT;
X RE_2: INTEGER;
X end record;
X variable V1: BIT;
X variable V2: BIT := '1';
X variable V3: REC_1;
X variable V4: ARAY_2;
X variable V5: ARAY_1;
X begin
X V1 := V2;
X V3.RE_1 := V2;
X V5(200) := V2 or V1;
X V4(1 to 5) := V5(21 to 25);
X return;
X end process;
X-- end block;
Xend BB_1;
*-*-END-of-s-08-4-0-0001a.vhdl-*-*
echo x - s-08-4-0-0002a.vhdl
sed 's/^X//' >s-08-4-0-0002a.vhdl <<'*-*-END-of-s-08-4-0-0002a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-08-1-5-0002A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that implicit type conversion is performed when the right-hand
X-- side value expression is of type universal integer or universal real.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
Xend E;
X
Xarchitecture AB of E is
X-- BB:block
X type NEW_INT is range -300 to 300;
X type NEW_REAL is range -300.0 to 300.0;
X begin
X process
X variable V1 : INTEGER;
X variable V2 : REAL;
X variable V3 : NEW_INT;
X variable V4 : NEW_REAL;
X variable V5 : INTEGER range 3 to 80;
X variable V6 : NEW_REAL range 3.0 to 80.0;
X begin
X V1 := 4;
X -- implicit type conversion from universal integer or universal real.
X V2 := 20.9;
X -- implicit type conversion from universal integer or universal real.
X V3 := 299;
X -- implicit type conversion from universal integer or universal real.
X V4 := -299.0;
X -- implicit type conversion from universal integer or universal real.
X V5 := 79;
X -- implicit type conversion from universal integer or universal real.
X V6 := 79.99;
X -- implicit type conversion from universal integer or universal real.
X end process;
X-- end block;
Xend AB;
*-*-END-of-s-08-4-0-0002a.vhdl-*-*
echo x - s-08-5-0-0001a.vhdl
sed 's/^X//' >s-08-5-0-0001a.vhdl <<'*-*-END-of-s-08-5-0-0001a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-08-1-6-0001A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that a procedure call without an actual parameter part is permitted
X-- (for procedure with no formal parameters or procedures whose formal
X-- parameters all have default values).
X-- JB (DB 7/12/85)
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xpackage P is
X procedure F ( A,B,C,D,E : integer := 0 ) ;
X procedure G ;
Xend P;
X
Xuse P.all ;
Xpackage body P is
X procedure F ( A,B,C,D,E : integer := 0 ) is
X begin
X return;
X end F;
X
X procedure G is
X begin
X null;
X end G;
Xend P;
X
Xuse P.all ;
Xpackage P is
X procedure F ( A,B,C,D,E : integer := 0 ) ;
X procedure G ;
Xend P ;
X
Xuse P.all ;
Xpackage body P is
Xprocedure F ( A,B,C,D,E : integer := 0 ) is
Xbegin
X return;
Xend F;
X
Xprocedure G is
Xbegin
X null;
Xend G;
Xend P ;
X
X--with package P;
X--with procedure F;
X--with procedure G;
Xuse P.F, P.G ;
Xentity E is
X port ( PT1, PT2 : INTEGER ) ;
Xend;
X
Xarchitecture BB of E is
X-- L_X_1: block
X begin
X process
X begin
X P.F;
X P.G;
X F;
X G;
X end process;
X-- end block;
Xend BB;
*-*-END-of-s-08-5-0-0001a.vhdl-*-*
echo x - s-08-7-0-0001a.vhdl
sed 's/^X//' >s-08-7-0-0001a.vhdl <<'*-*-END-of-s-08-7-0-0001a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-08-1-8-0001A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the choice "others" may stand for the full set of values of the
X-- expression in a case statement.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xpackage P is
X type E is (A,B,C,D);
X function F return BOOLEAN ;
Xend P;
X
Xuse P.all ;
Xpackage body P is
X function F return BOOLEAN is
X variable V : E := C;
X begin
X case V is
X when others => return TRUE;
X end case;
X end F;
Xend P;
X
Xentity E is
X port (PT:inout REAL) ;
Xend E;
X
Xarchitecture BB of E is
X-- L_X_1: block
X begin
X process
X variable V1,V2 : BOOLEAN := TRUE;
X begin
X case V1 or V2 is
X when others => return;
X end case;
X end process;
X-- end block;
Xend BB;
X
Xarchitecture AB of E is
X-- L_X_2: block
X begin
X process
X variable V : INTEGER;
X begin
X case V is
X when others => PT <= 0.0;
X end case;
X end process;
X-- end block;
Xend AB;
*-*-END-of-s-08-7-0-0001a.vhdl-*-*
echo x - s-08-7-0-0002a.vhdl
sed 's/^X//' >s-08-7-0-0002a.vhdl <<'*-*-END-of-s-08-7-0-0002a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-08-1-8-0002A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the case expression may be a complex static expression.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xpackage P is
X function F return BOOLEAN ;
Xend P;
X
Xuse P.all ;
Xpackage body P is
X function F return BOOLEAN is
X type I1 is range 0 to 10;
X variable V1 : I1 := 7;
X begin
X case V1 * 2 / 4 is
X when 0 to 5 => return TRUE;
X when 6 to 10 => return FALSE;
X end case;
X end F;
Xend P;
X
Xuse P.all ;
Xpackage P is
X function F return REAL ;
Xend P ;
X
Xuse P.all ;
Xpackage body P is
Xfunction F return REAL is
X subtype ST is INTEGER range 5 downto -2;
X variable V1 : ST ;
Xbegin
X case ST'(V1 - 3) is
X when 4 downto -1 => return 0.1;
X when -2 | 5 => return 9.0;
X end case;
X end F;
Xend P ;
X
Xentity E is
X port (PT:inout REAL) ;
Xend E;
X
Xarchitecture BB of E is
X-- L_X_1: block
X begin
X process
X subtype ST is INTEGER range 20 to 45;
X variable V1 : ST := 20;
X begin
X case V1>=20 and V1<30 is
X when TRUE => return;
X when FALSE => return;
X end case;
X end process;
X-- end block;
Xend BB;
X
Xarchitecture AB of E is
X-- L_X_2: block
X begin
X process
X type T1 is (U,V,W,X,Y,Z);
X variable V1 : T1 := Z;
X begin
X case V1<W or V1>X or V1=U is
X when TRUE => PT <= 0.9;
X when FALSE => PT <= 1.1;
X end case;
X end process;
X-- end block;
Xend AB;
*-*-END-of-s-08-7-0-0002a.vhdl-*-*
echo x - s-08-7-0-0003a.vhdl
sed 's/^X//' >s-08-7-0-0003a.vhdl <<'*-*-END-of-s-08-7-0-0003a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-08-1-8-0003A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that all discrete types may be used as case expressions. Check for
X-- enumeration (user-defined, predefined( character, bit, boolean))
X-- and integer types.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xpackage P is
X function F return BOOLEAN ;
Xend P;
X
Xuse P.all ;
Xpackage body P is
X function F return BOOLEAN is
X variable V1 : CHARACTER := '9';
X begin
X case V1 is
X when 'A' | 'Z' => return TRUE;
X when others => return FALSE;
X end case;
X end F;
Xend P;
X
Xuse P.all ;
Xpackage P is
X function F return REAL ;
Xend P ;
X
Xuse P.all ;
Xpackage body P is
Xfunction F return REAL is
X variable V1 : BIT;
Xbegin
X case V1 is
X when '0' => return 0.1;
X when '1' => return 9.0;
X end case;
X end F;
Xend P ;
X
Xentity E is
X port (PT:inout REAL) ;
Xend E;
X
Xarchitecture BB1 of E is
X-- L_X_1: block
X begin
X process
X variable V : BOOLEAN := TRUE;
X begin
X case V is
X when TRUE => return;
X when others => return;
X end case;
X end process;
X-- end block;
Xend BB1;
X
Xarchitecture BB of E is
X-- L_X_2: block
X begin
X process
X subtype ST is INTEGER range 20 to 45;
X variable V1 : ST := 20;
X begin
X case V1 is
X when 26 to 40 => return;
X when 20 to 25 => return;
X when 41 to 45 => return ;
X end case;
X end process;
X-- end block;
Xend BB;
X
Xarchitecture AB of E is
X-- L_X_3: block
X begin
X process
X type T1 is (U,V,W,X,Y,Z);
X variable V1 : T1 := Z;
X begin
X case V1 is
X when U | V | Y | Z => PT <= 0.9;
X when W | X => PT <= 1.1;
X end case;
X end process;
X-- end block;
Xend AB;
*-*-END-of-s-08-7-0-0003a.vhdl-*-*
echo x - s-08-7-0-0004a.vhdl
sed 's/^X//' >s-08-7-0-0004a.vhdl <<'*-*-END-of-s-08-7-0-0004a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-08-1-8-0004A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the choice "others" may stand for a null set of values.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xpackage P is
X type E is (A,B,C,D);
X function F return BOOLEAN ;
Xend P;
X
Xuse P.all ;
Xpackage body P is
X function F return BOOLEAN is
X variable V : E := C;
X begin
X case V is
X when A | C => return TRUE;
X when D => return FALSE;
X when B => return V=D;
X when others => return TRUE;
X end case;
X end F;
Xend P;
X
Xentity E is
X port (PT:inout REAL) ;
Xend E;
X
Xarchitecture BB of E is
X-- L_X_1: block
X begin
X process
X variable V1,V2 : BOOLEAN := TRUE;
X begin
X case V1 or V2 is
X when TRUE | FALSE => return;
X when others => return;
X end case;
X end process;
X-- end block;
Xend BB;
X
Xarchitecture AB of E is
X-- L_X_2: block
X begin
X process
X type E1 is (ONE,TWO);
X begin
X case ONE is
X when ONE => PT <= 0.1;
X when TWO => PT <= 2.0;
X when others => PT <= 0.0;
X end case;
X end process;
X-- end block;
Xend AB;
*-*-END-of-s-08-7-0-0004a.vhdl-*-*
echo x - s-08-8-0-0001a.vhdl
sed 's/^X//' >s-08-8-0-0001a.vhdl <<'*-*-END-of-s-08-8-0-0001a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-08-1-9-0001A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that all discrete types may be used as loop parameters. Check for
X-- enumeration (user-defined, predefined( character, bit, boolean) and integer
X-- types.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xuse P.all ;
Xpackage P is
X function F return REAL ;
Xend P ;
X
Xuse P.all ;
Xpackage body P is
Xfunction F return REAL is
X type E is (A,B,C,D);
Xbegin
X for I in D downto A loop
X return 63957.0;
X end loop;
X for I in BIT ' ('1') downto BIT'('0') loop
X return 3.5;
X end loop;
X for I in '~' downto 'z' loop
X return 9.4;
X end loop;
X for I in -10 to 10 loop
X return 0.0003;
X end loop;
X end F;
Xend P ;
X
Xentity E is
X port (PT:BOOLEAN) ;
Xend E;
X
Xarchitecture BB of E is
X-- L_X_1: block
X begin
X process
X type T is range 2 to NATURAL'HIGH ;
X variable V : NATURAL;
X variable V2 : T;
X begin
X for I in V2 to 9 * V2 loop
X return;
X end loop;
X for I in 'Z' downto 'A' loop
X return;
X end loop;
X for I in FALSE to TRUE loop
X return;
X end loop;
X for I in 10 downto V loop
X return;
X end loop;
X for I in abs (-10) downto 0 loop
X return;
X end loop;
X end process;
X-- end block;
Xend BB;
*-*-END-of-s-08-8-0-0001a.vhdl-*-*
echo x - s-08-8-0-0002a.vhdl
sed 's/^X//' >s-08-8-0-0002a.vhdl <<'*-*-END-of-s-08-8-0-0002a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-08-1-9-0002A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that non-static expressions are permitted as upper and lower bounds
X-- in the discrete range of loop parameter specifications. Special case:
X-- signal or variable names, function invocations, generic parameters.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xpackage P is
X type E is (W,X,Y);
X function F (P:E) return INTEGER ;
Xend P;
X
Xuse P.all ;
Xpackage body P is
X function F (P:E) return INTEGER is
X constant P1 : E := X ;
X variable V : E := P1;
X begin
X for I in W to P loop
X return 35;
X end loop;
X for I in Y downto V loop
X return 0;
X end loop;
X end F;
Xend P;
X
Xentity E is
X generic (G:NATURAL) ;
X port (PT,PT1:BOOLEAN) ;
X
Xend E;
X
Xarchitecture BB of E is
X-- L_X_1: block
X begin
X process
X constant F : NATURAL := 10 ;
X begin
X for I in PT downto not PT1 loop
X return;
X end loop;
X for I in G to 23 loop
X return;
X end loop;
X for I in F downto 0 loop
X return;
X end loop;
X end process;
X-- end block;
Xend BB;
*-*-END-of-s-08-8-0-0002a.vhdl-*-*
echo x - s-08-8-0-0003a.vhdl
sed 's/^X//' >s-08-8-0-0003a.vhdl <<'*-*-END-of-s-08-8-0-0003a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-08-1-9-0003A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that for static bounds the left boud may be less than, equal to, or
X-- greater than the right bound for either a "to" or "downto" loop parameter
X-- specification discrete range.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xuse P.all ;
Xpackage P is
X function F return REAL ;
Xend P ;
X
Xuse P.all ;
Xpackage body P is
Xfunction F return REAL is
X type E is (A,B,C,D);
Xbegin
X for I in A to D loop
X return 63957.0;
X end loop;
X for I in '1' downto BIT ' ('1') loop
X return 3.5;
X end loop;
X for I in '~' to 'z' loop
X return 9.4;
X end loop;
X end F;
Xend P ;
X
Xentity E is
X port (PT:BOOLEAN) ;
Xend E;
X
Xarchitecture BB of E is
X-- L_X_1: block
X begin
X process
X begin
X for I in 'A' downto 'Z' loop
X return;
X end loop;
X for I in TRUE to TRUE loop
X return;
X end loop;
X for I in 10 downto 9 mod 5 loop
X return;
X end loop;
X end process;
X-- end block;
Xend BB;
*-*-END-of-s-08-8-0-0003a.vhdl-*-*
echo x - s-08-8-0-0004a.vhdl
sed 's/^X//' >s-08-8-0-0004a.vhdl <<'*-*-END-of-s-08-8-0-0004a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-08-1-9-0004A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the loop label is optional.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xuse P.all ;
Xpackage P is
X function F return REAL ;
Xend P ;
X
Xuse P.all ;
Xpackage body P is
Xfunction F return REAL is
Xbegin
X L1: for I in 1 to 23 loop
X while I < 10 and 1 = 2 loop
X next L1;
X end loop;
X end loop L1;
X loop
X exit when 3 /= 8 / 2;
X end loop;
X return 3.5;
X end F;
Xend P ;
X
Xentity E is
X port (PT:BOOLEAN) ;
Xend E;
X
Xarchitecture BB of E is
X-- L_X_1: block
X begin
X process
X begin
X L1: while 1 /= 1 loop
X L2: loop
X exit L1 when TRUE;
X end loop L2;
X end loop L1;
X for I in 1 to 1 loop
X return;
X end loop;
X end process;
X-- end block;
Xend BB;
*-*-END-of-s-08-8-0-0004a.vhdl-*-*
echo x - s-08-9-0-0001a.vhdl
sed 's/^X//' >s-08-9-0-0001a.vhdl <<'*-*-END-of-s-08-9-0-0001a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-08-1-A-0001A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the when clause is optional.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
Xend E;
X
Xarchitecture AB of E is
X-- L_X_1: block
X begin
X process
X variable V1 : integer;
X variable V2 : boolean := TRUE;
X begin
X L1: loop
X V1 := 1;
X next L1;
X end loop L1;
X end process;
X-- end block;
Xend AB;
*-*-END-of-s-08-9-0-0001a.vhdl-*-*
echo x - s-08-9-0-0002a.vhdl
sed 's/^X//' >s-08-9-0-0002a.vhdl <<'*-*-END-of-s-08-9-0-0002a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-08-1-A-0002A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the loop label is optional.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
Xend E;
X
Xarchitecture AB of E is
X-- L_X_1: block
X begin
X process
X variable V1, V2 : integer;
X variable B1 : boolean := true;
X begin
X loop
X V2 := V1 - V2;
X next when B1;
X end loop;
X end process;
X-- end block;
X end AB;
*-*-END-of-s-08-9-0-0002a.vhdl-*-*
exit
--
Steve Grout @ MCC VLSI CAD Program, Austin TX. [512] 343-0860
ARPA: grout@mcc.arpa
UUCP: {ihnp4,seismo,harvard,gatech,pyramid}!ut-sally!im4u!milano!grout