[comp.lsi] Experience with "Electric"

singh@cs.glasgow.ac.uk (Mr Satnam Singh) (04/29/88)

Our site has recently accquired a VLSI design tool called "Electric".
This is written by Steven Rubin of Schlumberger (Palo Alto), who is the
author of a newish book called "Computer Aids for VLSI Design" (Addison-
Wesley).

Has anybody else been using this tool? If so, have they built any cell
libraries which they would like to share? Discussion of the merits of this
tool compared with the more established tools might be interesting.


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stevens@hplabsb.UUCP (Ken Stevens) (05/06/88)

I have been fortunate enough to become very familiar with Electric.  I
believe that it is an excellent design system, and the one which we have
chosen for our work.

A lot of this may be due to our "tall thin designer" approach, where one
designer is responsible for the specification down to the simulation,
layout and testing of a circuit.  One of Electric's features that I
particularly like is the internal knowledge of devices and networks.  This
aids in network comparisons from schematics, and also simplifies the
verification of the design through allowing simulators to be interactively
involked without having to go through the extract phase, or the input
specification phase.  The SPICE interface is a particularly nice example.
You can interconnect voltage sources and meters onto a layout or schematic,
and Electric will automatically generate the input deck, run SPICE, and
graph the results (although I prefer the standard SPICE output).  I can't
remember how to write SPICE decks anymore, and I don't miss it at all!  I
have never run into any differences between Electric's internal database
and what one gets from extraction, although it is good to do a final check
after extracting the circuit from CIF or some other format which contains
no connectivity information before going to fab.

The user interface is also very nice.  Almost everything can be redefined
and customized with macros.  There is also a very nice language interface.
I have written a circuit minimizer in lisp that takes a sum of products
input and produces schematics or a rough first pass of a layout in
Electric.

There is a very nice standard cell library that is distributed with
Electric (you may need to get a newer release) for the MOSIS scalable CMOS
design rules.

However, Electric is not perfect.  Particularly obvious is the lack of a
reasonable design rule checker (I reccomend getting DRACULA).  If you want
more feedback, just give me a call or send mail!

cheers		-Ken Stevens
(415) 857-3640 (unfortunately a lispm doesn't go with the phone number!)
stevens@hplabs.hp.com		hplabs!stevens