[comp.lsi] 10th Symposium on Computer Arithmetic

jmmuller@lip.ens-lyon.fr (Jean-Michel Muller) (04/12/91)

                     CALL FOR PARTICIPATION
       10th SYMPOSIUM ON COMPUTER ARITHMETIC   (ARITH-10)

                    Hotel "Alpotel" - Grenoble, France
                         June 25-28,1991
                                     
                           Sponsored by  :

      IEEE Computer Society (Technical Committee  on VLSI)
  Institut d'Informatique et de Mathematiques Appliquees de Grenoble (IMAG)
             Centre National de la Recherche Scientifique  (CNRS)


This file contains the preliminary program and a registration form.
Further information (list of hotels, plane & train schedules, maps 
of Grenoble...) may be obtained from :

Jean-Michel Muller (General Chairman),
Laboratoire LIP, Ecole Normale Superieure de Lyon,
46 Allee d'Italie, 69364 Lyon Cedex 07, FRANCE.
Phone : (+33) 72 72 82 29       Fax (+33) 72 72 80 80
E-mail : jmmuller@lip.ens-lyon.fr             
         jmmuller@frensl61.bitnet

Valerie Roger (Secretary)
Same address&Fax,
Phone : (+33) 72 72 80 37
E-mail : valerie@lip.ens-lyon.fr
valerie@frensl61.bitnet

                    I - PRELIMINARY PROGRAM


*** Tuesday, June 25, 1991

16 h 00 - 19 h 00	Registration 

19 h 00 - 19 h 15 	Opening
				Jean-Michel Muller, General Chairman
				David W. Matula and Peter Kornerup, Program Co-
				Chairmen

19 h 15 - 20 h 00	Invited Talk 
        "Arithmetic Standards : the long road"
				William J. Cody, Argonne National Laboratory

20 h 15			Buffet



*** Wednesday, June 26, 1991

08 h 00 - 08 h 30	Registration

Session 1: Number Systems (8:30 -- 10:15)
  Chair: Michel Scott, Dublin City University
  1.1 ``New Redundant Representations of Complex Numbers and Vectors''
      Jean Duprat, Yvan Herreros and Sylvanus Kla, LIP-IMAG,
      Ecole Normale Superieure de Lyon
  1.2 ``Analysis of Arithmetic Algorithms: A Statistical Study''
      F. Chatelin and V. Fraysse, CERFACS, Toulouse
  1.3 ``Representation of Numbers in Non-Classical Numeration Systems''
      Christiane Frougny, Universite Paris 8
  1.4 ``A Semantics for Exact Floating Point Operations''
      G. Bohlender and W. Walter, Universitat Karlsruhe, 
      P. Kornerup, Odense University and D.W. Matula, Southern
      Methodist University

	Coffee Break


Session 2: Multiplication (10:30 -- 12:15)
  Chair: Simon Knowles, INMOS, GB
  2.1 ``Shallow Multiplication Circuits''
      Michael S. Paterson and Uri Zwick, University of Warwick
  2.2 ``A Radix-4 Modular Multiplication Hardware Algorithm
      Efficient for Iterative Multiplication''
      Naofumi Takagi, Kyoto University
  2.3 ``High-Speed   Multiplier  Design   Using  Multi-Input Counter 
      and Compressor Circuits''
      Mayur Mehta and Vijay Parmar, Advanced Micro Devices
      and Earl Swartzlander, Jr., University of Texas at Austin
  2.4 ``A High-Radix Hardware Algorithm for Calculating the 
      Exponential M^^E Modulo N''
      Holger Orup, Aarhus University and P. Kornerup, Odense University

	Lunch

Session 3: Inner Products (14:00 -- 15:15)
  Chair: Svetoslav Markov, Bulgarian Academy of Science
  3.1 ``Arithmetic for Digital Neural Networks''
      D. Zhang, G.A. Jullien and W.C. Miller, University of Windsor
      and Earl Swartzlander, Jr., University of Texas at Austin
  3.2 ``Exact Accumulation of Floating-Point Numbers''
      Michael Muller, C.Rub and W.Rulling, Universitat des Saarlandes
  3.3 ``Fast Hardware Units for the Computation of Accurate Dot Products''
      Andreas Knofel, Universitat Karlsruhe


15 h 30 - 18 h 30	Sightseeing tour in Grenoble


*** THURSDAY, June 27, 1991

Session 4: Residue Arithmetic (8:30 -- 10:15)
  Chair: Magdy Bayoumi, University of Southwestern Louisiana
  4.1 ``A General Division in Residue Number System''
      Jen-Shiun Chiang and Mi Lu, Texas A&M University
  4.2 ``New Approach to Integer Division in Residue Number Systems''
      Dragan Gamberger, Rudjer Boskovic Institute, Zagreb
  4.3 ``Small Moduli Replications in the MRRNS''
      N.M. Wigley, G. Jullien, D. Reaume and W.C. Miller, University of Windsor
  4.4 ``Design of Residue Generators and Multi-Operand Modular Adders
      Using Carry-Save Adders''
      Stanislaw J. Piestrak, Institute of Eng. Cybernetics, Wroclaw

	Coffee Break

Session 5: Floating Point Range and Precision (10:30 -- 12:15)
  Chair: Renato Stefanelli, Politecnico di Milan
  5.1 ``Overflow/Underflow-Free Floating-Point Number Representations
      with Self-Delimiting Variable-Length Exponent Field''
      Hidetoshi Yokoo, Gunma University
  5.2 ``Implementation and Analysis of Extended SLI Operations''
      Peter R. Turner, U.S. Naval Academy
  5.3 ``Specifications for a Variable-Precision Arithmetic Coprocessor''
      T.E. Hull, M.S. Cohen and C.B. Hall, University of Toronto
  5.4 ``Algorithms for Arbitrary Precision Floating Point Arithmetic''
      Douglas M. Priest, University of California, Berkeley

	Lunch

Session 6: Adders I (14:00 -- 15:15)
  Chair: Tony Carter, University of Utah
  6.1 ``Designing Optimum Carry-Skip Adders''
      Vitit Kantabutra, Drexel University
  6.2 ``Delay Optimization of Carry-Skip and Block Carry-LookAhead Adders''
      P.K. Chan and  M.D.F. Schlag, UC Santa Cruz, C.D. Thomborson, 
      Univ. of  Minnesota, and V.G. Oklobdzija, IBM, T.J.Watson Research Center
  6.3 ``The Redundant Cell Adder''
      Tom Lynch and Earl Swartzlander, Jr., University of Texas at Austin

	Coffee Break

Session 7: Adders II (15:30 -- 16:20)
  Chair: Mary-Jane Irwin, Pennsylvania State University
  7.1 ``Optimal Purely Systolic Addition''
      Lars Kuhnel, Christian Albrechts Universitat, Kiel
  7.2 ``Constant Time Arbitrary Length Synchronous Binary Counters''
      J.E. Vuillemin, DEC, Paris Research Laboratory

16 h 25 - 17 h 40	Panel Session : "Future Trends of Computer 	
				Arithmetic"

18 h 30 - 23 h 00	Banquet Dinner 
			offered by the "Conseil General de l'Isere", will 
			take place at the "Prefecture de l'Isere"



*** FRIDAY, June 28, 1991

Session 8: Division (8:30 -- 10:15)
  Chair: George Taylor, MIPS Computer Systems
  8.1 ``Integer Division Using Reciprocals''
      Robert Alverson, Tera Computer Company
  8.2 ``Fast Division Using Accurate Quotient Approximations
      to Reduce the Number of Iterations''
      Derek C. Wong and Michael J. Flynn, Stanford University
  8.3 ``Simple Radix 2 Division and Square Root with Skipping 
      of Some Addition Steps''
      Paolo  Montuschi, Politechnico di Torino and 
      Luigi Ciminiera, Universita  degli Studi di L'Aquila
  8.4 ``A 160nS 54bit CMOS Division Implementation Using Self-Timing
      and Overlapped SRT Stages''
      Ted E. Williams, HaL Computer Systems and Mark A. Horowitz, Stanford
University

	Coffee Break

Session 9: GCD and Standard Functions (10:30 -- 12:15)
  Chair: S.M. Sedjelmaci, Universite D'Oran Es-Senia
  9.1 ``A Redundant Binary Euclidean GCD Algorithm''
      Shrikant N. Parikh, IBM and David W. Matula, Southern Methodist
University
  9.2 ``OCAPI: Architecture of a VLSI Coprocessor for the GCD
      and the Extended GCD of Large Numbers''
      Alain Guyot, Laboratoire TIM3/IMAG, Grenoble
  9.3 ``Table-Lookup Algorithms for Elementary Functions and Their Error
Analysis''
      Ping Tak Peter Tang, Argonne National Laboratory
  9.4 ``Accurate and Monotone Approximations of Some Transcendental Functions''
      Warren E. Ferguson, Jr. and T. Brightman, Cyrix Corporation

	Lunch

Session 10: On-Line and Signal Processing (14:00 -- 15:45)
  Chair: Henk J. Sips, Delft University of Technology
  10.1 ``Application of On-Line Arithmetic Algorithms to the SVD Computation:
       Preliminary Results''
       Paul K.-G. Tu, IBM and Milos D. Ercegovac, UCLA
  10.2 ``The CORDIC Householder Algorithm''
       Shen-Fu Hsiao and Jean-Marc Delosme , Yale University
  10.3 ``SVD by Constant-Factor-Redundant-CORDIC''
       Jeong-A  Lee, University  of Houston and  
       Tomas Lang,  Universitat Politecnica  de Catalunya
  10.4 ``Design and Implementation of a Floating-point Quasi-Systolic General
Purpose
       CORDIC Rotator for High-rate Parallel Data and Signal Processing''
       Alfons J. de Lange and Ed F. Deprettere, Delft University of Technology


15 h 45 - 16 h 00	Closing
Jean-Michel Muller, General Chairman.

---------------------------------------------------------------
               II - REGISTRATION FORM


To be returned before May 25, 1991 to :

Valerie ROGER
LIP - Ecole Normale Superieure de Lyon - 46, allee d'Italie
69364 Lyon cedex 07
e-mail : valerie@lip.ens-lyon.fr, valerie@frensl61.bitnet


Name, First name : .............................................
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Town, Zip Code.................................................................

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Registration fees :


          Before May 25, 1991            Late or on-site registration

IEEE Members              1200 FF                            1400 FF
(give member no)

Non members               1500 FF                            1800 FF

Students                  500 FF                              600 FF

(1 US Dollar = about 5.75 French Franc)

A copy of the proceedings, the Buffet of Thuesday June 25th, and the lunches
are included in these fees.
The banquet of thursday June 27th is offered by local organizations.

NOTE AUX FRANCAIS : Nous sommes desoles de ne pouvoir accepter les bons de 
commande.

Payments :

Will be accepted in cash or by banker's draft payable to :

J.M MULLER - Colloque IEEE Comp. Society