ekwok@mipos3.UUCP (06/30/87)
I realize that my previous posting looking for pointers to interconnect modelling may be too broad, so I am trying to narrow down to specific areas which is most immediately interesting to me. Specifically, I am studying the following issues: 1. estimates must be related to layout information. Is an estimate based on the number of fan-outs and not taking into account the geometry of the interconnect too crude for delay modelling? 2. Finite element analysis is too refined. Computation complexity for each configuration may be too expensive for analysis over all pieces of interconnect for a typical chip of the 100K+ devices complexity. Is there a simpler method? 3. traditional assumptions: that device output RC can be modelled by pullup/pulldown resistance of device and capacitance of interconnect, are they still valid (i.e. ignoring resitance in the interconnect) in technologies anticipated in the reasonably near future? 4. Does reliability concerns, such as electromigration design rules or modeling manufacturing defects (e.g. pin-holes) benefit from accurate models of interconnect? 5. Modelling contacts, in the same spirit as 2. What are the valid assumptions in the near term technologies (taking into consideration trends of relative resistivities of polysilicon and metals (- aluminum alloys?))? If you know about any publications relevant, or if you are currently working on any of these problems, I would like to learn from you. Again, mail path: {rest of world}!{hplabs,qantel,amdcad,decwrl}!intelca!mipos3!cadev2!ekwok reach out: 408-9877497. --