[comp.lsi] VLSI Testing, Questionnaire

guest@mcgill-vision.UUCP (Henry Cox) (10/13/88)

I'm interested in VLSI, particularly testing, in other universities.
I'd like to do a straw poll.  My questions to the net are:

- DO YOU ACTUALLY TEST THE CHIPS YOU HAVE FABRICATED?
    For what faults?  (functional, stuck-at, stuck-open, etc.)
    How do you generate your test patterns?  (which ATPG algorithm, etc.)

- WHAT TEST EQUIPMENT DO YOU HAVE?  (type, manufacturer, speed, pins, etc.)

- WHAT HAVE YOUR EXPERIENCES BEEN?  (yield, design errors,  sorts of faults
     in returned chips, etc.)

Reply to the net if you like, or send your answers to me 
(cox@spock.ee.mcgill.ca) - I'll take out any information which could be
used to find out who and where you are, and summarize for the net.  (I
will respond to all messages, so if you don't hear from me, try again).


(You can hit "n" now; what follows is what motivated me to ask,
and my answers to the above questions.)


Since you are still reading, I'm assuming you're interested...

MOTIVATION:
I became curious after attending a panel session on VLSI education 
at the International Test Conference (Sept. 12-14).  At the panel
session,  presentations were made by individuals from various schools
throughout the US, as well as by a fellow from the National Science
Foundation, in charge of MOSIS (the organization in the US that has
university designs fabricated).

I don't remember his figures, but MOSIS spent something like (US $)
600 000 last year on I-don't-know-how-many-chips (lots !).  His quote
was "WE DO NOT FABRICATE TIE CLIPS"; in order to have a chip fabricated,
some indication must be given how it is going to be tested - if this is 
not provided, the chip is not fabricated.  What, exactly, constitutes a
test plan was not specified (perhaps someone can enlighten me?); no follow
up is done by MOSIS to see if the chips actually were tested, whether or
not they worked, yield, etc.

The university presentations centered on the courses taught (content,
texts, projects, etc.), the CAD tools the school had, and the final project
designs produced over the past few years (microprocessors, etc.).  Most
mentioned that they covered some issues related to test in one of their
courses (what is a stuck-at fault?  How do you generate test patterns?
DFT, etc.).

Towards the end of the session, someone in the audience asked what
sort of hardware (logic analyser, etc.) everyone was using to test their
chips.  The moderator went first to the panel members, all of whom
remained silent.  One panelist, when pressed ("You DO test your chips,
don't you?"), closed his mouth firmly, put down his microphone, and
refused further comment.

The audience was no more cooperative, until some brave soul finally said
that his lab used some homemade stuff they built themselves.  Then one or
two other people spoke up and said that they had various models of
Tektronics logic analysers.  On the whole, however, the impression I got
was that very few people have test equipment, and that even fewer are
actually using it.

MY ANSWERS:
The McGill VLSI Design lab has quite a bit of Hewlett Packard test
equipment, most of which was given to us in a couple of equipment grants by
various government agencies, some of which we purchased on our own
(the money came from other research grants).  We now have:

 - 1 HP 8180A data generator + 1 HP 8181A data generator extender,
       for a total of 24 channels, 50 MHz, each channel 1024 bits deep
 - 1 HP 8182A data analyser, 28 channels, 50MHz, 1024 bits/channel
 - 1 HP 15414A tri-state unit, 2 control inputs (from data generator)
        with elementary boolean operations on them to determine if
        you really want to tristate them or not, bunches of 4 data
        generator channels plugged in to it to get tristate outputs.
 - 1 HP 6632A system DC power supply, controllable from HPIB bus, max
        voltage=20V, max current=5A, overcurrent protection, average
        current monitoring
 - 1 HP 15425A test head, 84 channels, 1/3 of which you can hook 2
        connectors to (one to generator and 1 to analyser, presumably)
 - HP 9816 microcomputer with 9133 hard disk unit, used to control
        all the above (somewhat painfully) - HP BASIC interpreter
 - 1 Tektronics 2235 100 MHz oscilloscope
 - 4000 pages of useless boring manuals

The equipment is used primarily in the lab and project portions of a
VLSI testing course, and for a couple of Masters thesis projects.
The labs are basically to become familiar with the equipment (AC
parametrics, functional test, characterization of off-the-shelf
circuits), followed by a project portion to develop a test strategy,
generate test vectors, test the chip, and write a report.  Standard
projects have been: functional test of a Z80, test complex gates of
MPP (more later), etc.

We in Canada are not part of MOSIS, but the Canadian Microelectronics
Corporation (CMC) performs a similar function.  CMC is the agent who
collects university designs, organizes them into multi-project chips,
and sends them to Northern Telecom, which then fabricates the chips free
of charge.

Last year (winter 1987), the VLSI Design II course designed a processing
element of an array processor (similar to the Goodyear MPP).  The PE was
fabricated and returned.  The chip was tested using design verification
patterns, as well as algorithmically generated ones (for both stuck-at and
stuck-open faults).  In testing, we discovered an design error in one of
the cells which resulted in something that looked a lot like a stuck-open
fault.  Due to leakage, we were able to test the chip at about 1 KHz (it was
intended to operate at 10 MHz); aside from the "stuck open" design
error, one NAND gate was put where a NOR gate was supposed to be, making
part of the circuit untestable.  Other than that, it worked.  The errors
were corrected, and the chip resubmitted.  This spring, the processing
element was redesigned, and an array (6 x 4) of them was submitted for
fabrication (not back yet).  

I would continue, but I expect I've gone on too long already.  I
apologize if I have misinterpreted what other people have said or have
gotten my facts wrong.  Feel free to correct me.  Politeness counts :-).

				Henry Cox (cox@spock.ee.mcgill.ca)
				VLSI Design Lab
				McGill University
				Montreal

< I have no connection to any of the companies or organizations          >
< mentioned here, except the McGill VLSI design lab.  I speak only for   >
< myself - the opinions expressed here do not represent those of the     >
< McGill VLSI design lab or anyone or anything else, animal, vegetable,  >
< or mineral.						                 >