ayman@caen.engin.umich.edu (Ayman Kayssi) (02/10/91)
Is there a simple formula that relates the effective resistance of a mosfet to its dimensions and the rise time of the waveform at its gate ( when the transistor is the pull down of an inverter ) and possibly the capacitive load at its drain ? The simplest formula relates Reff to the dimensions, but that's not accurate enough. Thanks. <Ayman> -- [ Ayman Issam Kayssi | Email: ] [ Advanced Computer Architecture Lab. | ayman@eecs.umich.edu ] [ EECS Dept., Univ. of Michigan, Ann Arbor | ayman@caen.engin.umich.edu ]
pi@quark.isi.edu (Jen-I Pi) (02/11/91)
In article <1991Feb9.201136.18151@engin.umich.edu>, ayman@caen.engin.umich.edu (Ayman Kayssi) writes: |> |> Is there a simple formula that relates the effective |> resistance of a mosfet to its dimensions and the rise |> time of the waveform at its gate ( when the transistor |> is the pull down of an inverter ) and possibly the |> capacitive load at its drain ? |> The simplest formula relates Reff to the dimensions, but |> that's not accurate enough. |> Thanks. |> <Ayman> See "Explicit Formulation of Delays in CMOS Data Paths", IEEE Journal of Solid-State Circuits, Vol. 23, No. 5, pp. 1257-1264, 1988. for detail... To be brief, Equation (8) gives the effective resistance of a minimum size NMOS transistor in a chain of n inverters. Equation (11) gives the effective resistance for the TG (transmission gate) configuration. Hope this helps, ----- Jen-I pi@vlsi-cad.isi.edu :-) MOSIS Project, USC/ISI 4676 Admiralty way Marina del Rey, CA 90292-6695 (213)822-1511 x640