grout@sunspot.stars.flab.Fujitsu.JUNET (Steve Grout) (07/13/88)
This is Chapter 14 of a 1076-1987 VHDL test suite which was
translated from an 7.2 VHDL version test suite developed by
Intermetrics under funding by the DoD. These tests have been
verified todate mainly against a VHDL 'recognizer' so they may
yet have problems with VHDL semantics. They consist of two
classes of tests,
ERROR Tests: - names which start with 'e' should result in VHDL errors
at the spot where there is a comment about error being expected.
SIMPLE Tests: - names which start with 's' should analyze or compile cleanly.
These tests are being shared back to industry in hopes of getting together
a joint set of tests, checked out and verified, which we can all use to
make sure our various VHDL CAD tools work correctly.
Your comments and especially constructive criticism is urgently requested
via any way we can get it. All replies and resulting changes/updates will
be posted back to the same places these tests were originally posted.
Thanks for your support!
--Steve Grout, MCC CAD Program. (512)338-3516, grout@mcc.com
---- Cut Here and unpack ----
#!/bin/sh
#
# This is a 'shar' archive. Cut out everything above the line
# and unpack them with /bin/sh, i.e., using a command like:
# % sh < {the contents of this message after cutting}
#
#
echo "--------------------------------------------------"
echo "Starting to extract Chapter 14 of a 1076-1987 VHDL"
echo " translated DoD/Intermetrics test suite...."
echo "--------------------------------------------------"
echo x - TEST-SYNOPSIS.text
sed 's/^X//' >TEST-SYNOPSIS.text <<'*-*-END-of-TEST-SYNOPSIS.text-*-*'
X: 14-Predefined
X------------------------------------------------------------------------
X
X
X------------------------------------------------------------------------
X Paragraph: Predefined Attributes - B.1 --> 14.1
X------------------------------------------------------------------------
X e-14-1-0-0001a.vhdl
X e-14-1-0-0002a.vhdl
X e-14-1-0-0003a.vhdl
X e-14-1-0-0003b.vhdl
X e-14-1-0-0004a.vhdl
X e-14-1-0-0004b.vhdl
X e-14-1-0-0004c.vhdl
X e-14-1-0-0005a.vhdl
XTest: e-14-1-0-0005b.vhdl
X-- Check that the base type of X in T'POS(X), T'SUCC(X) and T'PRED(X) must
X-- be the base type of T.
X-- also see E-14-1-0-0005A.VHD
XTest: e-14-1-0-0006a.vhdl
X-- Check that X in T'VAL(X) must be of an integer type.
XTest: e-14-1-0-0007a.vhdl
X-- Check that T'SUCC(X) gives an error if X = T'BASE'HIGH. Check that T'PRED(X)
X-- gives an error if X = T'BASE'LOW.
XTest: e-14-1-0-0008a.vhdl
X-- Check that the T' cannot be omitted in T'POS(X), T'VAL(X), T'SUCC(X), and
X-- T'PRED(X).
XTest: e-14-1-0-0009a.vhdl
X-- Check that N in A'LEFT(N), A'RIGHT(N), A'HIGH(N), A'LOW(N), A'RANGE(N), and
X-- A'LENGTH(N) must be a static expression of type universal integer.
XTest: e-14-1-0-0010a.vhdl
X-- Check that N in A'LEFT(N), A'RIGHT(N), A'HIGH(N), A'LOW(N), A'RANGE(N), and
X-- A'LENGTH(N) not exceed the dimensionality of A.
X-- Also checks that N in A'LEFT(N), A'RIGHT(N), A'HIGH(N), A'LOW(N),
X-- A'RANGE(N), and A'LENGTH(N) cannot be <= zero.
XTest: e-14-1-0-0011a.vhdl
X-- Check that A in A'LEFT(N), A'RIGHT(N), A'HIGH(N), A'LOW(N), A'RANGE(N), and
X-- A'LENGTH(N) cannot be a scalar object, a scalar value, a record object, a
X-- record type, or an unconstrained array type.
XTest: e-14-1-0-0012a.vhdl
X-- Check that A' cannot be omitted in A'LEFT(N), A'RIGHT(N), A'HIGH(N),
X-- A'LOW(N), A'RANGE(N), and A'LENGTH(N).
XTest: e-14-1-0-0013a.vhdl
X-- Check that S in S'DELAYED, S'STABLE, and S'QUIET must be a signal.
XTest: e-14-1-0-0014a.vhdl
X-- Check that T in S'DELAYED(T), S'STABLE(T), and S'QUIET(T)
X-- must be a generic expression of type time.
XTest: e-14-1-0-0015a.vhdl
X-- Check that B in B'CHILDLESS and B'STRUCTURE must be an architectural body.
XTest: e-14-1-0-0016a.vhdl
X-- Check that S'LAST_VALUE does not denote a signal.
XTest: s-14-1-0-0001a.vhdl
X-- Check that BASE, LEFT, RIGHT, HIGH, LOW, POS, VAL, SUCC, PRED, LENGTH,
X-- DELAYED, STABLE, QUIET, LAST_VALUE, CHILDLESS, and STRUCTURE are
X-- not reserved words.
XTest: s-14-1-0-0002a.vhdl
X-- Check that the range of T in T'BASE is any type or subtype.
X-- Apparently there is no legal use of T'BASE where T is a type or subtype of
X-- record or unconstrained array type as there are no predefined attributes
X-- which accept a record type prefix and user defined attributes cannot take
X-- a type prefix.
XTest: s-14-1-0-0003a.vhdl
X-- Check that the value of T'BASE is correct.
X-- Apparently there is no legal use of T'BASE where T is a type or subtype of
X-- record or unconstrained array type as there are no predefined attributes
X-- which accept a record type prefix and user defined attributes cannot take
X-- a type prefix.
XTest: s-14-1-0-0004a.vhdl
X-- Check that the range of T in T'LEFT, T'RIGHT, T'HIGHT, AND T'LOW
X-- is any scalar or constrained array subtype or any array object or
X-- array value, also see S-14-1-0-0004B.VHD.
XTest: s-14-1-0-0004b.vhdl
X-- Check that the range of T in T'LEFT, T'RIGHT, T'LOW and i]T'HIGH
X-- is any scalar or constrained array subtype, or any array object or
X-- array value, see also SC100004A.
XTest: s-14-1-0-0005a.vhdl
X-- Check that the value of T'LEFT and T'RIGHT is correct.
XTest: s-14-1-0-0006a.vhdl
X-- Check that the value of T'LOW and T'HIGH is correct (special case where
X-- T'LOW = T'RIGHT)
XTest: s-14-1-0-0007a.vhdl
X-- Check that the range of T in T'POS(X), T'VAL(X), T'SUCC(X) and T'PRED(X)
X-- is any discrete or physical type or subtype.
X-- also see S-14-1-0-0007B.VHD and S-14-1-0-0007C.VHD
XTest: s-14-1-0-0007b.vhdl
X-- Check that the range of T in T'POS(X), T'VAL(X), T'SUCC(X) and T'PRED(X)
X-- is any discrete or physical type or subtype.
X-- also see SC100007A and SC100007C.
XTest: s-14-1-0-0007c.vhdl
X-- Check that the range of T in T'POS(X), T'VAL(X), T'SUCC(X) and T'PRED(X)
X-- is any discrete or physical type or subtype.
X-- also see S-14-1-0-0007A.VHD and S-1
4-1-0-0007B.VHD
XTest: s-14-1-0-0008a.vhdl
X-- Check that the value of T'POS(X) is correct.
XTest: s-14-1-0-0009a.vhdl
X-- Check that the value of T'VAL(X) is correct.
XTest: s-14-1-0-0010a.vhdl
X-- Check that T'SUCC(X) and T'PRED(X) give the correct values. In particular,
X-- check that if S is a subtype of T then S'SUCC(X) does not give an error if
X-- S'HIGH = X but S'BASE'HIGH /= X, and that S'PRED(X) does not give an error
X-- if S'LOW = X but S'BASE'LOW /= X.
XTest: s-14-1-0-0011a.vhdl
X-- Check that A in A'LEFT(N), A'RIGHT(N), A'HIGH(N), A'LOW(N), A'RANGE(N), and
X-- A'LENGTH(N) can be an array object, an array value, or a constrained array
X-- type or subtype.
XTest: s-14-1-0-0012a.vhdl
X-- Check that if A is not a scalar type or subtype and (N) is omitted in
X-- A'LEFT(N), A'RIGHT(N), A'HIGH(N), A'LOW(N) or A'LENGTH(N) the default is N=1.
XTest: s-14-1-0-0013a.vhdl
X-- Check that if (N) is omitted in A'RANGE(N) or A'LENGTH(N) the default
X-- is N=1
X-- There is no good way to test for A'LENGTH since A'LENGTH is not a
X-- static expression, and A'LENGTH is always of type UNIVERSAL INTEGER.
XTest: s-14-1-0-0015a.vhdl
X-- Check that the range of S in S'DELAYED, S'STABLE, and S'QUIET is
X-- any object of class signal or of mode "in", "buffer", or "inout" denoted
X-- by the static signal name S.
XTest: s-14-1-0-0015b.vhdl
X-- Check that the range of S in S'LAST_VALUE is any object of class signal
X-- or any signal element.
XTest: s-14-1-0-0016a.vhdl
X-- Check that S'DELAYED(T), S'STABLE(T), AND S'QUIET(T) denote signals.
X
X------------------------------------------------------------------------
X Paragraph: Predefined Types and Subtypes --> Package STANDARD - B.2 --> 14.2
X------------------------------------------------------------------------
XTest: e-14-2-0-0001a.vhdl
X-- Check that the parameters of predefined function TMIN and TMAX must
X-- be of type TIME.
XTest: s-14-2-0-0001a.vhdl
X-- Check that identifiers declared in package STANDARD are not reserved words.
XTest: s-14-2-0-0002a.vhdl
X-- Check that both predefined functions TMIN and TMAX return a value of type
X-- TIME predefined in package STANDARD.
X
X------------------------------------------------------------------------
X Paragraph: Package TEXTIO:
X------------------------------------------------------------------------
X not in 7.2 --> 14.3
X
X
X
X
*-*-END-of-TEST-SYNOPSIS.text-*-*
echo x - e-14-1-0-0005b.vhdl
sed 's/^X//' >e-14-1-0-0005b.vhdl <<'*-*-END-of-e-14-1-0-0005b.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-14-1-0-0005B.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the base type of X in T'POS(X), T'SUCC(X) and T'PRED(X) must
X-- be the base type of T.
X-- also see E-14-1-0-0005A.VHD
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- ------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
X port (PT:BOOLEAN) ;
Xend E;
X
Xarchitecture BB of E is
X-- L_X_1: block
X begin
X process
X type E is (A,B,C,D);
X type P is range 1 to 24
X units
X U;
X X=3U;
X Y=2X;
X end units;
X variable V1 : INTEGER;
X begin
X V1 := E'VAL(C); -- ERROR : X in T'VAL(X) must be integer type
X V1 := CHARACTER'VAL('Z'); -- ERROR : X in T'VAL(X) must be integer type
X V1 := BOOLEAN'VAL(FALSE); -- ERROR : X in T'VAL(X) must be integer type
X V1 := P'VAL(Y); -- ERROR : X in T'VAL(X) must be integer type
X return;
X end process;
X-- end block;
Xend BB;
X
Xarchitecture AB of E is
X-- L_X_2: block
X signal S1 : INTEGER;
X begin
X process
X begin
X S1 <= INTEGER'VAL(23965.0); -- ERROR : X in T'VAL(X) must be integer type
X end process;
X-- end block;
Xend AB;
*-*-END-of-e-14-1-0-0006a.vhdl-*-*
echo x - e-14-1-0-0007a.vhdl
sed 's/^X//' >e-14-1-0-0007a.vhdl <<'*-*-END-of-e-14-1-0-0007a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-14-1-0-0007A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that T'SUCC(X) gives an error if X = T'BASE'HIGH. Check that T'PRED(X)
X-- gives an error if X = T'BASE'LOW.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
X port (PT:BOOLEAN) ;
Xend E;
X
Xarchitecture BB of E is
X-- L_X_1: block
X begin
X process
X type E is (A,B,C,D);
X type P is range 1 to 24
X units
X U;
X X=3U;
X Y=2X;
X end units;
X variable V1 : INTEGER;
X begin
X V1 := E'SUCC(D); -- ERROR : X in T'SUCC(X) cannot be T'BASE'HIGH
X V1 := CHARACTER'PRED(NUL); -- ERROR : X in T'PRED(X) cannot be T'BASE'LOW
X V1 := BOOLEAN'SUCC(TRUE); -- ERROR : X in T'SUCC(X) cannot be T'BASE'HIGH
X V1 := P'PRED(U); -- ERROR : X in T'PRED(X) cannot be T'BASE'LOW
X return;
X end process;
X-- end block;
Xend BB;
X
Xarchitecture AB of E is
X-- L_X_1: block
X signal S1 : INTEGER;
X begin
X process
X begin
X S1 <= BIT'SUCC('1'); -- ERROR : X in T'SUCC(X) cannot be T'BASE'HIGH
X end process;
X-- end block;
Xend AB;
*-*-END-of-e-14-1-0-0007a.vhdl-*-*
echo x - e-14-1-0-0008a.vhdl
sed 's/^X//' >e-14-1-0-0008a.vhdl <<'*-*-END-of-e-14-1-0-0008a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-14-1-0-0008A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the T' cannot be omitted in T'POS(X), T'VAL(X), T'SUCC(X), and
X-- T'PRED(X).
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
X port (PT:BOOLEAN) ;
Xend E;
X
Xarchitecture BB of E is
X-- L_X_1: block
X begin
X process
X subtype ST is INTEGER range -5 to 20;
X type E is (A,B,C,D);
X type P is range 1 to 24
X units
X U;
X X=3U;
X Y=2X;
X end units;
X variable V1 : static ST;
X variable V4 : E;
X variable V5 : P;
X begin
X V1 := POS(C); -- ERROR : T in T'POS cannot be omitted
X V4 := VAL(A); -- ERROR : T in T'VAL cannot be omitted
X V5 := SUCC(Y); -- ERROR : T in T'SUCC cannot be omitted
X return;
X end process;
X-- end block;
Xend BB;
X
Xarchitecture AB of E is
X-- L_X_2: block
X signal S1 : REAL;
X begin
X process
X begin
X S1 <= PRED(2.10000); -- ERROR : T in T'PRED cannot be omitted
X end process;
X-- end block;
Xend AB;
*-*-END-of-e-14-1-0-0008a.vhdl-*-*
echo x - e-14-1-0-0009a.vhdl
sed 's/^X//' >e-14-1-0-0009a.vhdl <<'*-*-END-of-e-14-1-0-0009a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-14-1-0-0009A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that N in A'LEFT(N), A'RIGHT(N), A'HIGH(N), A'LOW(N), A'RANGE(N), and
X-- A'LENGTH(N) must be a static expression of type universal integer.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
X port (PT:BOOLEAN) ;
Xend E;
X
Xarchitecture BB of E is
X-- L_X_1: block
X begin
X process
X type R is
X record
X RE : REAL;
X end record;
X type E is (A,B,C,D);
X subtype T is CHARACTER range 'A' to 'C';
X type AR1 is array (1 to 1,2 downto 1,'A' to 'Z') of BOOLEAN;
X type AR2 is array (2 to 4,TRUE downto FALSE) of INTEGER range 0 to 4;
X type AR3 is array (-2 downto -37,A to D,2 to 37,2 downto -2) of R;
X type AR4 is array (BIT'('1') downto BIT'('0')) of AR1;
X variable V1 : AR3;
X variable V2 : AR4;
X variable V3 : AR2;
X variable V4 : BOOLEAN;
X variable V5 : REAL;
X variable V6 : CHARACTER;
X variable V7 : E;
X variable V8 : INTEGER range AR3'RANGE(3.0);--ERROR:non-integer A'RANGE(N)
X variable V9 : BIT;
X constant C1 : REAL := 1.0;
Xbegin
X V7 := V1'LEFT(TRUE); -- ERROR : N in A'LEFT(N) must be integer
X V9 := V2'RIGHT(C1); -- ERROR : N in A'RIGHT(N) must be integer
X V8 := V3'HIGH(T'('A')); -- ERROR : N in A'HIGH(N) must be integer
X V4 := AR2'LOW(B); -- ERROR : N in A'LOW(N) must be integer
X V8 := V1'LENGTH(V8); -- ERROR : N in A'LENGTH(N) must be static integer
X return;
X end process;
X-- end block;
Xend BB;
X
Xarchitecture AB of E is
X-- L_X_2: block
X type AR1 is array (7 downto 0,4 to 15) of BIT;
X signal S1 : INTEGER;
X signal S2 : BOOLEAN;
X signal S3 : BIT;
X begin
X process
X begin
X S2 <= FALSE;
X S1 <= AR1'RIGHT(S2); -- ERROR : N in A'RIGHT(N) must be integer
X S3 <= AR1'LEFT(2#10#); -- ERROR : N in A'LEFT(N) must be integer
X S3 <= AR1'HIGH(S1); -- ERROR : N in A'HIGH(N) must be integer
X S1 <= AR1'LENGTH(1);
X end process;
X-- end block;
Xend AB;
*-*-END-of-e-14-1-0-0009a.vhdl-*-*
echo x - e-14-1-0-0010a.vhdl
sed 's/^X//' >e-14-1-0-0010a.vhdl <<'*-*-END-of-e-14-1-0-0010a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-14-1-0-0010A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that N in A'LEFT(N), A'RIGHT(N), A'HIGH(N), A'LOW(N), A'RANGE(N), and
X-- A'LENGTH(N) not exceed the dimensionality of A.
X-- Also checks that N in A'LEFT(N), A'RIGHT(N), A'HIGH(N), A'LOW(N),
X-- A'RANGE(N), and A'LENGTH(N) cannot be <= zero.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
X port (PT:BOOLEAN) ;
Xend E;
X
Xarchitecture BB of E is
X-- L_X_1: block
X begin
X process
X type R is
X record
X RE : REAL;
X end record;
X type E is (A,B,C,D);
X type AR1 is array (1 to 1,2 downto 1,'A' to 'Z') of BOOLEAN;
X type AR2 is array (2 to 4,TRUE downto FALSE) of INTEGER range 0 to 4;
X type AR3 is array (-2 downto -37,2 to 37,2 downto -2,A to D) of R;
X type AR4 is array (-3 downto -4) of AR1;
X variable V1 : AR3;
X variable V2 : AR4;
X variable V3 : AR2;
X variable V4 : BOOLEAN;
X variable V5 : REAL;
X variable V6 : CHARACTER range AR1'RANGE(5);--ERROR:exceeds dimensionality
X variable V7 : E;
X variable V8 : INTEGER;
Xbegin
X V7 := V1'LEFT(5); -- ERROR : N in A'LEFT(N) exceeds dimensionality of A
X V5 := V2'RIGHT(2); -- ERROR : N in A'RIGHT(N) exceeds dimensionality of A
X V8 := V3'HIGH(0); -- ERROR : N in A'HIGH(N) cannot be <= 0
X V4 := AR2'LOW(-3); -- ERROR : N in A'LOW(N) cannot be <= 0
X V8 := AR4'LENGTH(6); -- ERROR : N in A'LENGTH(N) exceeds dimensionality
X return;
X end process;
X-- end block;
Xend BB;
X
Xarchitecture AB of E is
X-- L_X_2: block
X type AR1 is array (7 downto 0) of BIT;
X signal S1 : AR1;
X signal S2 : INTEGER;
X begin
X process
X begin
X S2 <= S1'LENGTH(9); -- ERROR : N in A'LENGTH(N) exceeds dimensionality of A
X end process;
X-- end block;
Xend AB;
*-*-END-of-e-14-1-0-0010a.vhdl-*-*
echo x - e-14-1-0-0011a.vhdl
sed 's/^X//' >e-14-1-0-0011a.vhdl <<'*-*-END-of-e-14-1-0-0011a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-14-1-0-0011A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that A in A'LEFT(N), A'RIGHT(N), A'HIGH(N), A'LOW(N), A'RANGE(N), and
X-- A'LENGTH(N) cannot be a scalar object, a scalar value, a record object, a
X-- record type, or an unconstrained array type.
X-- JB (DB 7/18/85)
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
X port (PT:BOOLEAN) ;
Xend E;
X
Xarchitecture BB of E is
X-- L_X_1: block
X begin
X process
X subtype ST is INTEGER range -5 to 20;
X type R is
X record
X RE : ST;
X end record;
X type AR is array (POSITIVE range <> ) of ST;
X type E is (A,B,C,D);
X type P is range 1 to 24
X units
X U;
X X=3U;
X Y=2X;
X end units;
X variable V1 : ST;
X variable V2 : R;
X variable V3 : E;
X variable V4 : P;
X variable V5 : ST range V2'RANGE(4); --ERROR:non-array object in A'RANGE(N)
X begin
X V1 := V1'LEFT(3); -- ERROR : A in A'LEFT(N) cannot be non-array value
X V2 := V2'RIGHT(11); -- ERROR : A in A'RIGHT(N) cannot be non-array value
X V3 := AR'HIGH(7); -- ERROR : A in A'HIGH(N) cannot be unconstrained array
X V4 := V4'LOW(2); -- ERROR : A in A'LOW(N) cannot be non-array value
X V5 := V4'LENGTH(8);-- ERROR : A in A'LENGTH(N) cannot be non-array object
X return;
X end process;
X-- end block;
Xend BB;
X
Xarchitecture AB of E is
X-- L_X_2: block
X signal S1 : REAL;
X begin
X process
X begin
X S1 <= S1'HIGH(1); -- ERROR : A in A'HIGH(N) cannot be non-array object
X end process;
X-- end block;
Xend AB;
X
Xuse P.all ;
Xpackage body P is
Xfunction F (P:BIT) return CHARACTER is
X variable V : BIT;
Xbegin
X V := P'LEFT(1); -- ERROR : T in T'LEFT(X) cannot be non-array object
X for I in BIT'('1') downto '0' loop
X V := I'LOW(1); -- ERROR : T in T'RIGHT(X) cannot be non-array object
X end loop;
X return 'Q';
X end F;
Xend P ;
*-*-END-of-e-14-1-0-0011a.vhdl-*-*
echo x - e-14-1-0-0012a.vhdl
sed 's/^X//' >e-14-1-0-0012a.vhdl <<'*-*-END-of-e-14-1-0-0012a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-14-1-0-0012A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that A' cannot be omitted in A'LEFT(N), A'RIGHT(N), A'HIGH(N),
X-- A'LOW(N), A'RANGE(N), and A'LENGTH(N).
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
X port (PT:BOOLEAN) ;
Xend E;
X
Xarchitecture BB of E is
X-- L_X_1: block
Xbegin
Xprocess
X type R is
X record
X RE : REAL;
X end record;
X type E is (A,B,C,D);
X type AR1 is array (1 to 1,2 downto 1,'A' to 'Z') of BOOLEAN;
X type AR2 is array (2 to 4,TRUE downto FALSE) of INTEGER range 0 to 4;
X type AR3 is array (-2 downto -37,2 to 37,2 downto -2,A to D) of R;
X type AR4 is array (-3 downto -4) of AR1;
X variable V1 : AR3;
X variable V2 : AR4;
X variable V3 : AR2;
X variable V4 : BOOLEAN range RANGE(2);--ERROR:A' cannot be omitted
X variable V5 : REAL;
X variable V6 : CHARACTER;
X variable V7 : E;
X variable V8 : INTEGER;
Xbegin
X V7 := LEFT(4); -- ERROR : A' in A'LEFT(N) cannot be omitted
X V5 := RIGHT(1); -- ERROR : A' in A'RIGHT(N) cannot be omitted
X V8 := HIGH(2); -- ERROR : A' in A'HIGH(N) cannot be omitted
X V4 := LOW(2); -- ERROR : A' in A'LOW(N) cannot be omitted
X V8 := LENGTH(3);-- ERROR : A' in A'LENGTH(N) cannot be omitted
X return;
X end process;
X-- end block;
Xend BB;
X
Xarchitecture AB of E is
X-- L_X_1: block
X
X type AR1 is array (7 downto 0) of BIT;
X signal S1 : AR1;
X signal S2 : INTEGER;
X begin
X process
X begin
X S2 <= RIGHT(1); -- ERROR : A in A'RIGHT(N) cannot be omitted
X end process;
X-- end block;
Xend AB;
*-*-END-of-e-14-1-0-0012a.vhdl-*-*
echo x - e-14-1-0-0013a.vhdl
sed 's/^X//' >e-14-1-0-0013a.vhdl <<'*-*-END-of-e-14-1-0-0013a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-14-1-0-0013A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that S in S'DELAYED, S'STABLE, and S'QUIET must be a signal.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
X port (PT: BOOLEAN) ;
Xend E;
X
Xarchitecture BB of E is
X-- L_X_1: block
X begin
X process
X variable I2 : integer range 1 to 1000 := 10;
X variable R2: real range 1.1 to 5.5 := 1.3;
X variable CH2 : character := 'c';
X constant C2 : integer := 2;
X variable B1 : boolean;
X
X begin
X B1 := (I2'DELAYED(0ns) = 4);
X-- ERROR: OBJECT OF 'DELAYED MUST BE AS SIGNAL;
X
X B1 := (R2'DELAYED(0ns) =0.5);
X-- ERROR: OBJECT OF 'DELAYED MUST BE AS SIGNAL;
X
X if (C2'QUIET) then
X-- ERROR: OBJECT OF 'QUIET MUST BE AS SIGNAL;
X return;
X
X elsif (C2'STABLE) THEN
X-- ERROR: OBJECT OF 'STABLE MUST BE AS SIGNAL;
X return;
X
X elsif (CH2'QUIET) then
X-- ERROR: OBJECT OF 'QUIET MUST BE AS SIGNAL;
X return;
X
X elsif (CH2'STABLE) then
X-- ERROR: OBJECT OF 'STABLE MUST BE AS SIGNAL;
X return;
X else return;
X end if;
X end process;
X-- end block;
X end BB;
*-*-END-of-e-14-1-0-0013a.vhdl-*-*
echo x - e-14-1-0-0014a.vhdl
sed 's/^X//' >e-14-1-0-0014a.vhdl <<'*-*-END-of-e-14-1-0-0014a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-14-1-0-0014A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that T in S'DELAYED(T), S'STABLE(T), and S'QUIET(T)
X-- must be a generic expression of type time.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
Xend E;
X
Xarchitecture BB of E is
X-- L_X_1: block
X component C1 port (C1 : inout Bit);
X end component ;
X
X begin
X process
X
X variable R2 : real ;
X
X begin
X
X if (C1'QUIET('A')) then
X-- ERROR: 'QUIET MUST HAVE A GENERIC EXPRESSION OF TYPE TIME.
X return;
X elsif (C1'STABLE(R2)) then
X-- ERROR: 'STABLE MUST HAVE A GENERIC EXPRESSION OF TYPE TIME.
X return;
X else
X C1'DELAYED(20) <= 6.6;
X-- ERROR: 'DELAYED MUST HAVE A GENERIC EXPRESSION OF TYPE TIME.
X end if;
X end process;
X-- end block;
Xend BB;
*-*-END-of-e-14-1-0-0014a.vhdl-*-*
echo x - e-14-1-0-0015a.vhdl
sed 's/^X//' >e-14-1-0-0015a.vhdl <<'*-*-END-of-e-14-1-0-0015a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-14-1-0-0015A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that B in B'CHILDLESS and B'STRUCTURE must be an architectural body.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xpackage PA is
X
X procedure P is
X begin
X null;
X end P;
Xend PA;
X
X-- with package PA;
Xuse PA.all;
Xentity E is
Xend E;
X
Xarchitecture DB of E is
X-- L_X_1: block
X begin
X process
X begin
X IF (P'CHILDLESS) then
X-- ERROR THE OBJECT OF CHILDLESS AND STRUCTURE MUST BE A ARCHITECTURE BODY
X return;
X ELSIF (P'STRUCTURE) then
X-- ERROR THE OBJECT OF CHILDLESS AND STRUCTURE MUST BE A ARCHITECTURE BODY
X return;
X end if;
X
X IF (E'CHILDLESS) then
X-- ERROR THE OBJECT OF CHIDLESS AND STRUCTURE MUST BE A ARCHITECTURE BODY
X return;
X ELSIF (E'STRUCTURE) then
X-- ERROR THE OBJECT OF CHIDLESS AND STRUCTURE MUST BE A ARCHITECTURE BODY
X return;
X end if;
X
X end process;
X-- end block;
X end DB;
*-*-END-of-e-14-1-0-0015a.vhdl-*-*
echo x - e-14-1-0-0016a.vhdl
sed 's/^X//' >e-14-1-0-0016a.vhdl <<'*-*-END-of-e-14-1-0-0016a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-14-1-0-0016A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that S'LAST_VALUE does not denote a signal.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
Xend E;
X
Xarchitecture AB of E is
X-- BB : block
X component XA port (A : INTEGER);
X end component ;
X signal S1 : INTEGER;
X signal S2 : INTEGER;
X begin
X S1 <= S2'LAST_VALUE'LAST_VALUE;
X -- ERROR : S2'LAST_VALUE does not denote a signal name
X X1 : XA port map ( A => S2'LAST_VALUE );
X -- ERROR : S2'LAST_VALUE does not denote a signal name
X-- end block;
Xend AB;
*-*-END-of-e-14-1-0-0016a.vhdl-*-*
echo x - e-14-2-0-0001a.vhdl
sed 's/^X//' >e-14-2-0-0001a.vhdl <<'*-*-END-of-e-14-2-0-0001a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-14-2-0-0001A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the parameters of predefined function TMIN and TMAX must
X-- be of type TIME.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
X
Xentity E is
Xend E;
X
Xarchitecture BB of E is
X-- L_X_1: block
X begin
X process
X type ODD_time is range 0 to 1e18
X units
X mm;
X cm = 10 mm;
X dm = 10 cm;
X ym = 100 dm;
X end units;
X
X variable WTIME : ODD_time;
X variable R1,R2 : REAL ;
X variable ANS : BOOLEAN;
X variable TIM : TIME;
X
X begin
X TIM := TMIN('A','B');
X -- ERROR TMIN AND TMAX PARAMETERS MUST BE OF TYPE TIME
X
X TIM := TMAX('A','B');
X -- ERROR TMIN AND TMAX PARAMETERS MUST BE OF TYPE TIME
X
X TIM := TMAX(ANS,ANS);
X -- ERROR TMIN AND TMAX PARAMETERS MUST BE OF TYPE TIME
X
X TIM := TMIN (R1,R2);
X -- ERROR TMIN AND TMAX PARAMETERS MUST BE OF TYPE TIME
X
X end process;
X-- end block;
Xend BB;
*-*-END-of-e-14-2-0-0001a.vhdl-*-*
echo x - s-14-1-0-0001a.vhdl
sed 's/^X//' >s-14-1-0-0001a.vhdl <<'*-*-END-of-s-14-1-0-0001a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-14-1-0-0001A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that BASE, LEFT, RIGHT, HIGH, LOW, POS, VAL, SUCC, PRED, LENGTH,
X-- DELAYED, STABLE, QUIET, LAST_VALUE, CHILDLESS, and STRUCTURE are
X-- not reserved words.
X-- JB (DB 7/31/85)
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
X port (PT:BOOLEAN) ;
Xend E;
X
Xarchitecture BB of E is
X-- L_X_1: block
X begin
X process
X variable BASE, LEFT, RIGHT : REAL := 3.9;
X variable HIGH, LOW, POS, VAL : INTEGER := 17;
X variable SUCC, PRED, LENGTH : CHARACTER := '0';
X begin
X BASE := LEFT + RIGHT;
X VAL := HIGH * LOW - POS;
X if PRED='A' then
X LENGTH := SUCC;
X end if;
X end process;
X-- end block;
Xend;
*-*-END-of-s-14-1-0-0001a.vhdl-*-*
echo x - s-14-1-0-0002a.vhdl
sed 's/^X//' >s-14-1-0-0002a.vhdl <<'*-*-END-of-s-14-1-0-0002a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-14-1-0-0002A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the range of T in T'BASE is any type or subtype.
X-- Apparently there is no legal use of T'BASE where T is a type or subtype of
X-- record or unconstrained array type as there are no predefined attributes
X-- which accept a record type prefix and user defined attributes cannot take
X-- a type prefix.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
X
Xentity E is
X port (PT:BOOLEAN) ;
Xend E;
X
Xarchitecture BB of E is
X-- L_X_1: block
X signal S1 : BIT_VECTOR (0 to 15);
X signal S2 : INTEGER ;
X begin
X process
X subtype ST is INTEGER range -5 to 20;
X type E is (A,B,C,D);
X type P is range 1 to 24
X units
X U;
X X=3U;
X Y=2X;
X end units;
X type AR1 is array (-4 to -1,C downto A,BIT'BASE'LEFT to BIT'BASE'RIGHT)
X of ST;
X type AR2 is array ('X' to 'Z',TRUE downto FALSE) of INTEGER;
X variable V1 : INTEGER;
X variable V2 : BIT;
X variable V3 : E;
X variable V4 : P;
X variable V5 : REAL;
X variable V6 : BOOLEAN;
X begin
X V3 := E'BASE'LEFT;
X V2 := AR1'BASE'RIGHT(3);
X V5 := REAL'BASE'HIGH;
X V6 := AR2'BASE'LOW(2);
X V1 := E'BASE'POS(C);
X V1 := ST'BASE'VAL(1);
X V1 := INTEGER'BASE'PRED(1);
X V4 := P'BASE'SUCC(2Y);
X V1 := AR1'BASE'LENGTH(2);
X S2 <= 8;
X return;
X end process;
X-- end block;
Xend BB;
X
*-*-END-of-s-14-1-0-0002a.vhdl-*-*
echo x - s-14-1-0-0003a.vhdl
sed 's/^X//' >s-14-1-0-0003a.vhdl <<'*-*-END-of-s-14-1-0-0003a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-14-1-0-0003A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the value of T'BASE is correct.
X-- Apparently there is no legal use of T'BASE where T is a type or subtype of
X-- record or unconstrained array type as there are no predefined attributes
X-- which accept a record type prefix and user defined attributes cannot take
X-- a type prefix.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
X
Xentity E is
X port (PT:BOOLEAN) ;
Xend E;
X
Xarchitecture BB of E is
X-- L_X_1: block
X begin
X process
X subtype BTRUE is BOOLEAN range TRUE to TRUE;
X subtype ST is INTEGER range -5 to 20;
X type E is (A,B,C,D);
X type P is range 1 to 24
X units
X U;
X X=3U;
X Y=2X;
X end units;
X variable V1 : INTEGER;
X variable V2 : BIT;
X variable V3 : E;
X variable V4 : P;
X variable V5 : REAL;
X variable V6 : BOOLEAN;
X variable V7 : BTRUE;
X begin
X case V7 is
X when (
X (E'BASE'LEFT=E'LEFT)
X and (REAL'BASE'HIGH=REAL'HIGH)
X and (E'BASE'POS(C)=E'POS(C))
X and (ST'BASE'VAL(1)=INTEGER'VAL(1))
X and (INTEGER'BASE'PRED(1)=INTEGER'PRED(1))
X and (P'BASE'SUCC(2Y)=P'SUCC(2Y))
X ) => return;
X end case;
X end process;
X-- end block;
Xend BB;
*-*-END-of-s-14-1-0-0003a.vhdl-*-*
echo x - s-14-1-0-0004a.vhdl
sed 's/^X//' >s-14-1-0-0004a.vhdl <<'*-*-END-of-s-14-1-0-0004a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-14-1-0-0004A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the range of T in T'LEFT, T'RIGHT, T'HIGHT, AND T'LOW
X-- is any scalar or constrained array subtype or any array object or
X-- array value, also see S-14-1-0-0004B.VHD.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
X port (PT:BOOLEAN) ;
Xend E;
X
Xarchitecture BB of E is
X-- L_X_1: block
X signal S1 : INTEGER;
X begin
X process
X subtype ST1 is INTEGER range -5 to 20;
X type E is (A,B,C,D);
X subtype ST2 is E range C to D;
X type P is range 1 to 24
X units
X U;
X X=3U;
X Y=2X;
X end units;
X subtype ST3 is P;
X variable V1 : INTEGER;
X variable V2 : BIT;
X variable V3 : E;
X variable V4 : P;
X variable V5 : REAL;
X variable V6 : BOOLEAN;
X begin
X V3 := E'LEFT;
X V5 := REAL'BASE'RIGHT;
X V3 := ST2'LEFT;
X V1 := ST1'BASE'RIGHT;
X V4 := P'BASE'RIGHT;
X V4 := ST3'LEFT;
X V6 := BOOLEAN'RIGHT;
X V2 := BIT'LEFT;
X S1 <= ST1'BASE'RIGHT;
X return;
X end process;
X-- end block;
Xend BB;
*-*-END-of-s-14-1-0-0004a.vhdl-*-*
echo x - s-14-1-0-0004b.vhdl
sed 's/^X//' >s-14-1-0-0004b.vhdl <<'*-*-END-of-s-14-1-0-0004b.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-14-1-0-0004B.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the range of T in T'LEFT, T'RIGHT, T'LOW and i]T'HIGH
X-- is any scalar or constrained array subtype, or any array object or
X-- array value, see also SC100004A.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
X port (PT:BOOLEAN) ;
Xend E;
X
Xarchitecture BB of E is
X-- L_X_1: block
X signal S1 : INTEGER;
X begin
X process
X subtype ST1 is INTEGER range -5 to 20;
X type E is (A,B,C,D);
X subtype ST2 is E range C to D;
X type P is range 1 to 24
X units
X U;
X X=3U;
X Y=2X;
X end units;
X subtype ST3 is P;
X variable V1 : INTEGER;
X variable V2 : BIT;
X variable V3 : E;
X variable V4 : P;
X variable V5 : REAL;
X variable V6 : BOOLEAN;
X begin
X V3 := E'LOW;
X V5 := REAL'BASE'HIGH;
X V3 := ST2'LOW;
X V1 := ST1'BASE'HIGH;
X V4 := P'BASE'HIGH;
X V4 := ST3'LOW;
X V6 := BOOLEAN'HIGH;
X V2 := BIT'LOW;
X S1 <= ST1'BASE'HIGH;
X return;
X end process;
X-- end block;
Xend BB;
X
*-*-END-of-s-14-1-0-0004b.vhdl-*-*
echo x - s-14-1-0-0005a.vhdl
sed 's/^X//' >s-14-1-0-0005a.vhdl <<'*-*-END-of-s-14-1-0-0005a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-14-1-0-0005A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the value of T'LEFT and T'RIGHT is correct.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
X port (PT:BOOLEAN) ;
Xend E;
X
Xarchitecture BB of E is
X-- L_X_1: block
X begin
X process
X subtype BTRUE is BOOLEAN range TRUE to TRUE;
X subtype ST1 is INTEGER range -5 to 20;
X type E is (A,B,C,D);
X subtype ST2 is E range C to D;
X type P is range 1 to 24
X units
X U;
X X=3U;
X Y=2X;
X end units;
X subtype ST3 is P;
X variable V1 : INTEGER;
X variable V2 : BIT;
X variable V3 : E;
X variable V4 : P;
X variable V5 : REAL;
X variable V6 : BOOLEAN;
X variable V7 : BTRUE;
X constant MAXINT : INTEGER := INTEGER'HIGH;
X constant MAXREAL : REAL := REAL'HIGH;
X begin
X case V7 is
X when (
X (E'LEFT=A)
X and (REAL'BASE'RIGHT=MAXREAL)
X and (ST2'LEFT=C)
X and (ST1'BASE'RIGHT=MAXINT)
X and (P'BASE'RIGHT=4Y)
X and (ST3'LEFT=U)
X and (BOOLEAN'RIGHT=TRUE)
X and (BIT'LEFT='0')
X ) => return;
X end case;
X end process;
X-- end block;
Xend BB;
*-*-END-of-s-14-1-0-0005a.vhdl-*-*
echo x - s-14-1-0-0006a.vhdl
sed 's/^X//' >s-14-1-0-0006a.vhdl <<'*-*-END-of-s-14-1-0-0006a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-14-1-0-0006A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the value of T'LOW and T'HIGH is correct (special case where
X-- T'LOW = T'RIGHT)
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
X port (PT:BOOLEAN) ;
Xend E;
X
Xarchitecture BB of E is
X-- L_X_1: block
X begin
X process
X subtype BTRUE is BOOLEAN range TRUE to TRUE;
X subtype ST1 is INTEGER range -5 to 20;
X type DOWN is range 15 downto -5;
X type E is (A,B,C,D);
X subtype ST2 is E range C to D;
X type P is range 1 to 24
X units
X U;
X X=3U;
X Y=2X;
X end units;
X subtype ST3 is P range X to X;
X variable V7 : BTRUE;
X begin
X case V7 is
X when (
X (E'LOW=A)
X and (REAL'BASE'HIGH=REAL'BASE'RIGHT)
X and (ST2'LOW=C)
X and (ST1'HIGH=ST1'RIGHT)
X and (P'BASE'HIGH=4Y)
X and (ST3'LOW=ST3'HIGH) -- SPECIAL CASE : T'LOW = T'RIGHT
X and (BOOLEAN'HIGH=TRUE)
X and (DOWN'HIGH=DOWN'LEFT)
X and (BIT'LOW='0')
X ) => return;
X end case;
X end process;
X-- end block;
Xend BB;
*-*-END-of-s-14-1-0-0006a.vhdl-*-*
echo x - s-14-1-0-0007a.vhdl
sed 's/^X//' >s-14-1-0-0007a.vhdl <<'*-*-END-of-s-14-1-0-0007a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-14-1-0-0007A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the range of T in T'POS(X), T'VAL(X), T'SUCC(X) and T'PRED(X)
X-- is any discrete or physical type or subtype.
X-- also see S-14-1-0-0007B.VHD and S-14-1-0-0007C.VHD
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
X port (PT:BOOLEAN) ;
Xend E;
X
Xarchitecture BB of E is
X-- L_X_1: block
X signal S1 : INTEGER;
X begin
X process
X subtype ST1 is INTEGER range -5 to 20;
X type E is (A,B,C,D);
X subtype ST2 is E range C to D;
X type P is range 1 to 24
X units
X U;
X X=3U;
X Y=2X;
X end units;
X subtype ST3 is P;
X variable V1 : INTEGER;
X begin
X V1 := E'POS(A);
X V1 := ST2'POS(D);
X V1 := ST1'BASE'POS(-5);
X V1 := P'BASE'POS(2Y);
X V1 := ST3'POS(X);
X V1 := BOOLEAN'POS(TRUE);
X V1 := BIT'POS('0');
X S1 <= INTEGER'BASE'POS(20000);
X return;
X end process;
X-- end block;
Xend BB;
X
*-*-END-of-s-14-1-0-0007a.vhdl-*-*
echo x - s-14-1-0-0007b.vhdl
sed 's/^X//' >s-14-1-0-0007b.vhdl <<'*-*-END-of-s-14-1-0-0007b.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-14-1-0-0007B.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the range of T in T'POS(X), T'VAL(X), T'SUCC(X) and T'PRED(X)
X-- is any discrete or physical type or subtype.
X-- also see SC100007A and SC100007C.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
X port (PT:BOOLEAN) ;
Xend E;
X
Xarchitecture BB of E is
X-- L_X_1: block
X signal S1 : integer;
X begin
X process
X subtype ST1 is INTEGER range -5 to 20;
X type E is (A,B,C,D);
X subtype ST2 is E range C to D;
X type P is range 1 to 24
X units
X U;
X X=3U;
X Y=2X;
X end units;
X subtype ST3 is P;
X variable V1 : INTEGER;
X variable V2 : E;
X variable V3 : P;
X variable V4 : BOOLEAN;
X variable V5 : BIT;
X begin
X V2 := E'VAL(1);
X V2 := ST2'VAL(2);
X V1 := ST1'BASE'VAL(1);
X V3 := P'BASE'VAL(12);
X V3 := ST3'VAL(3);
X V4 := BOOLEAN'VAL(0);
X V5 := BIT'VAL(1);
X S1 <= INTEGER'BASE'VAL(20000);
X return;
X end process;
X-- end block;
Xend BB;
*-*-END-of-s-14-1-0-0007b.vhdl-*-*
echo x - s-14-1-0-0007c.vhdl
sed 's/^X//' >s-14-1-0-0007c.vhdl <<'*-*-END-of-s-14-1-0-0007c.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-14-1-0-0007C.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the range of T in T'POS(X), T'VAL(X), T'SUCC(X) and T'PRED(X)
X-- is any discrete or physical type or subtype.
X-- also see S-14-1-0-0007A.VHD and S-14-1-0-0007B.VHD
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
X port (PT:BOOLEAN) ;
Xend E;
X
Xarchitecture BB of E is
X-- L_X_1: block
X signal S1 : INTEGER;
X begin
X process
X subtype ST1 is INTEGER range -5 to 20;
X type E is (A,B,C,D);
X subtype ST2 is E range C to D;
X type P is range 1 to 24
X units
X U;
X X=3U;
X Y=2X;
X end units;
X subtype ST3 is P;
X variable V1 : INTEGER;
X variable V2 : E;
X variable V3 : P;
X variable V4 : BOOLEAN;
X variable V5 : BIT;
X begin
X V2 := E'SUCC(A);
X V2 := ST2'PRED(D);
X V1 := ST1'BASE'SUCC(5);
X V3 := P'BASE'PRED(2Y);
X V3 := ST3'SUCC(X);
X V4 := BOOLEAN'PRED(TRUE);
X V5 := BIT'SUCC('0');
X S1 <= INTEGER'BASE'PRED(20000);
X return;
X end process;
X-- end block;
Xend BB;
*-*-END-of-s-14-1-0-0007c.vhdl-*-*
echo x - s-14-1-0-0008a.vhdl
sed 's/^X//' >s-14-1-0-0008a.vhdl <<'*-*-END-of-s-14-1-0-0008a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-14-1-0-0008A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the value of T'POS(X) is correct.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
X port (PT:BOOLEAN) ;
Xend E;
X
Xarchitecture BB of E is
X-- L_X_1: block
X begin
X process
X subtype BTRUE is BOOLEAN range TRUE to TRUE;
X subtype ST1 is INTEGER range -5 to 20;
X type E is (A,B,C,D);
X subtype ST2 is E range C to D;
X type P is range 1 to 24
X units
X U;
X X=3U;
X Y=2X;
X end units;
X subtype ST3 is P;
X variable V1 : INTEGER;
X variable V2 : BTRUE;
X begin
X case V2 is
X when (
X (E'POS(A)=0)
X and (ST2'POS(D)=3)
X and (ST1'POS(-5)=-5)
X and (P'BASE'POS(2Y)=12)
X and (ST3'POS(X)=3)
X and (BOOLEAN'POS(TRUE)=1)
X and (BIT'POS('0')=0)
X ) => return;
X end case;
X end process;
X-- end block;
Xend BB;
*-*-END-of-s-14-1-0-0008a.vhdl-*-*
echo x - s-14-1-0-0009a.vhdl
sed 's/^X//' >s-14-1-0-0009a.vhdl <<'*-*-END-of-s-14-1-0-0009a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-14-1-0-0009A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the value of T'VAL(X) is correct.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
X port (PT:BOOLEAN) ;
Xend E;
X
Xarchitecture BB of E is
X-- L_X_1: block
X begin
X process
X subtype BTRUE is BOOLEAN range TRUE to TRUE;
X subtype ST1 is INTEGER range -5 to 20;
X type E is (A,B,C,D);
X subtype ST2 is E range C to D;
X type P is range 1 to 24
X units
X U;
X X=3U;
X Y=2X;
X end units;
X subtype ST3 is P;
X variable V1 : INTEGER;
X variable V2 : BTRUE;
X begin
X case V2 is
X when (
X (E'VAL(0)=A)
X and (ST2'VAL(3)=D)
X and (ST1'BASE'VAL(1)=1)
X and (P'BASE'VAL(12)=2Y)
X and (ST3'VAL(3)=X)
X and (BOOLEAN'VAL(1)=TRUE)
X and (BIT'VAL(0)='0')
X ) => return;
X end case;
X end process;
X-- end block;
Xend BB;
*-*-END-of-s-14-1-0-0009a.vhdl-*-*
echo x - s-14-1-0-0010a.vhdl
sed 's/^X//' >s-14-1-0-0010a.vhdl <<'*-*-END-of-s-14-1-0-0010a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-14-1-0-0010A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that T'SUCC(X) and T'PRED(X) give the correct values. In particular,
X-- check that if S is a subtype of T then S'SUCC(X) does not give an error if
X-- S'HIGH = X but S'BASE'HIGH /= X, and that S'PRED(X) does not give an error
X-- if S'LOW = X but S'BASE'LOW /= X.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
X port (PT:BOOLEAN) ;
Xend E;
X
Xarchitecture BB of E is
X-- L_X_1: block
X begin
X process
X subtype BTRUE is BOOLEAN range TRUE to TRUE;
X subtype ST1 is INTEGER range -5 to 20;
X type E is (A,B,C,D);
X subtype ST2 is E range C to D;
X type P is range 1 to 24
X units
X U;
X X=3U;
X Y=2X;
X end units;
X subtype ST3 is P range X to Y;
X variable V1 : INTEGER;
X variable V2 : E;
X variable V3 : P;
X variable V4 : BOOLEAN;
X variable V5 : BIT;
X variable V6 : BTRUE;
X begin
X case V6 is
X when (
X (E'SUCC(A)=B)
X and (ST2'PRED(D)=C)
X and (ST1'SUCC(20)=21)-- SPECIAL CASE : S'HIGH = X /= S'BASE'HIGH
X and (ST3'PRED(X)=2U) -- SPECIAL CASE : S'LOW = X /= S'BASE'LOW
X and (P'SUCC(5U)=Y)
X and (BOOLEAN'PRED(TRUE)=FALSE)
X and (BIT'SUCC('0')='1')
X ) => return;
X end case;
X end process;
X-- end block;
Xend BB;
*-*-END-of-s-14-1-0-0010a.vhdl-*-*
echo x - s-14-1-0-0011a.vhdl
sed 's/^X//' >s-14-1-0-0011a.vhdl <<'*-*-END-of-s-14-1-0-0011a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-14-1-0-0011A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that A in A'LEFT(N), A'RIGHT(N), A'HIGH(N), A'LOW(N), A'RANGE(N), and
X-- A'LENGTH(N) can be an array object, an array value, or a constrained array
X-- type or subtype.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
X port (PT:BOOLEAN) ;
Xend E;
X
Xarchitecture BB of E is
X-- L_X_1: block
X begin
X process
X subtype BTRUE is BOOLEAN range TRUE to TRUE;
X type E is (A,B,C,D,F,G,H);
X type AR1 is array (POSITIVE range <>) of E;
X subtype ST1 is AR1;
X subtype ST2 is AR1 (1 to 10);
X type R is
X record
X RE : REAL;
X end record;
X type AR2 is array (A to D,TRUE downto FALSE,8 to 12,'X' to 'Z') of R;
X subtype ST3 is AR2;
X variable V0 : BTRUE;
X variable V1 : AR1(10 to 20);
X variable V2 : ST1(5 to 10);
X variable V3 : ST2;
X variable V4 : AR2;
X variable V5 : ST3;
X subtype ST4 is E range V4'RANGE(1);
X type AR3 is array (-5 to 5) of ST4;
X variable V6 : AR3;
X variable V7 : INTEGER;
X variable V8 : BOOLEAN;
X variable V9 : E;
X begin
X V7 := ST2'LEFT(1);
X V8 := AR2'RIGHT(2);
X V9 := ST3'HIGH(1);
X V7 := V1'LOW(1);
X V9 := V4'LOW(1);
X V9 := V4'HIGH(1);
X V7 := V3'LENGTH(1);
X V7 := V4'LENGTH(3);
X V7 := V5'LENGTH(4);
X return;
X end process;
X-- end block;
Xend BB;
*-*-END-of-s-14-1-0-0011a.vhdl-*-*
echo x - s-14-1-0-0012a.vhdl
sed 's/^X//' >s-14-1-0-0012a.vhdl <<'*-*-END-of-s-14-1-0-0012a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-14-1-0-0012A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that if A is not a scalar type or subtype and (N) is omitted in
X-- A'LEFT(N), A'RIGHT(N), A'HIGH(N), A'LOW(N) or A'LENGTH(N) the default is N=1.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
X port (PT:BOOLEAN) ;
Xend E;
X
Xarchitecture BB of E is
X-- L_X_1: block
X begin
X process
X type E is (A,B,C,D,F,G,H);
X type AR1 is array (POSITIVE range <>) of E;
X subtype ST1 is AR1;
X subtype ST2 is AR1 (1 to 10);
X type R is
X record
X RE : REAL;
X end record;
X type AR2 is array (A to D,TRUE downto FALSE,8 to 12,'X' to 'Z') of R;
X subtype ST3 is AR2;
X variable V1 : AR1(10 to 20);
X variable V2 : ST1(5 to 10);
X variable V3 : ST2;
X variable V4 : AR2;
X variable V5 : ST3;
X subtype ST4 is E range V4'RANGE;
X type AR3 is array(-5 to 5) of ST4;
X variable V6 : AR3;
X begin
X if (
X (ST2'LEFT=ST2'LEFT(1))
X and (AR2'RIGHT=AR2'RIGHT(1))
X and (ST3'HIGH=ST3'HIGH(1))
X and (V1'LOW=V1'LOW(1))
X and (V6'LOW=V6'LOW(1))
X and (V6'HIGH=V6'HIGH(1))
X and (V3'LENGTH=V3'LENGTH(1))
X and (V4'LENGTH=V4'LENGTH(1))
X and (V5'LENGTH=V5'LENGTH(1))
X ) then return;
X -- if the default value of N in 'LEFT(N) ... is not 1 a type
X -- error will occur.
X end if;
X end process;
X-- end block;
Xend BB;
*-*-END-of-s-14-1-0-0012a.vhdl-*-*
echo x - s-14-1-0-0013a.vhdl
sed 's/^X//' >s-14-1-0-0013a.vhdl <<'*-*-END-of-s-14-1-0-0013a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-14-1-0-0013A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that if (N) is omitted in A'RANGE(N) or A'LENGTH(N) the default
X-- is N=1
X-- There is no good way to test for A'LENGTH since A'LENGTH is not a
X-- static expression, and A'LENGTH is always of type UNIVERSAL INTEGER.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xuse P.all ;
Xpackage body P is
X type SQUID is range 4.0 to 1000.0;
X type A_ARRAY is array
X (INTEGER range 1 to 10,
X BIT range '1' downto '0',
X BOOLEAN range FALSE to FALSE,
X CHARACTER range 'A' to 'Z') of SQUID;
X type B_ARRAY is array (INTEGER range <>) of BIT;
X subtype B_CONSTRAINED is B_ARRAY(10 downto 1);
X
X subtype B1 is INTEGER range A_ARRAY'RANGE;
X -- A_ARRAY'RANGE should be the same as A_ARRAY'RANGE(1)
X -- type error will occur if not true
X subtype B2 is INTEGER range A_ARRAY'RANGE(1);
X
X procedure P1 ( A : B1 ) is
X variable BOOL : BOOLEAN;
X begin
X BOOL := A = B_CONSTRAINED'LENGTH;
X -- if this is not equivalent to B_CONSTRAINED'LENGTH(1) an error
X -- will occur since B_CONSTRAINED has only one dimension
X BOOL := A = B_CONSTRAINED'LENGTH(1);
X end P1;
Xend P;
*-*-END-of-s-14-1-0-0013a.vhdl-*-*
echo x - s-14-1-0-0015a.vhdl
sed 's/^X//' >s-14-1-0-0015a.vhdl <<'*-*-END-of-s-14-1-0-0015a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-14-1-0-0015A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the range of S in S'DELAYED, S'STABLE, and S'QUIET is
X-- any object of class signal or of mode "in", "buffer", or "inout" denoted
X-- by the static signal name S.
X-- JB (DB 7/18/85)
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
X port (PT1:in STRING;PT2:buffer TIME;PT3:inout BOOLEAN) ;
Xend E;
X
Xarchitecture BB of E is
X-- L_X_1: block
X signal S1 : INTEGER;
X signal S2 : CHARACTER;
X signal S3 : BIT;
X signal S4 : REAL;
X begin
X process
X begin
X PT3 <= PT1'STABLE;
X PT2 <= PT2'DELAYED;
X PT3 <= PT3'QUIET;
X if (S1'STABLE and S1'QUIET) then
X S1 <= S1'DELAYED;
X end if;
X if (S2'STABLE and S2'QUIET) then
X S2 <= S2'DELAYED;
X end if;
X if (S3'STABLE and S3'QUIET) then
X S3 <= S3'DELAYED;
X end if;
X if (S4'STABLE and S4'QUIET) then
X S4 <= S4'DELAYED;
X end if;
X end process;
X-- end block;
Xend BB;
*-*-END-of-s-14-1-0-0015a.vhdl-*-*
echo x - s-14-1-0-0015b.vhdl
sed 's/^X//' >s-14-1-0-0015b.vhdl <<'*-*-END-of-s-14-1-0-0015b.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-14-1-0-0015B.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the range of S in S'LAST_VALUE is any object of class signal
X-- or any signal element.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
Xend E;
X
Xarchitecture BB of E is
X-- L_X_1: block
X
X signal S1 : integer;
X signal S2 : real;
X signal S3 : character;
X signal S4 : boolean;
X
X begin
X process
X
X begin
X
X S1 <= 5;
X S2 <= 5.5;
X S3 <= 'A';
X S4 <= TRUE;
X
X S1 <= S1'LAST_VALUE;
X
X S2 <= S2'LAST_VALUE;
X
X S3 <= S3'LAST_VALUE;
X
X S4 <= S4'LAST_VALUE;
X
X end process;
X-- end block;
Xend BB;
*-*-END-of-s-14-1-0-0015b.vhdl-*-*
echo x - s-14-1-0-0016a.vhdl
sed 's/^X//' >s-14-1-0-0016a.vhdl <<'*-*-END-of-s-14-1-0-0016a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-14-1-0-0016A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that S'DELAYED(T), S'STABLE(T), AND S'QUIET(T) denote signals.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
Xend E;
X
Xarchitecture AB of E is
X-- BB : block
X component XIN port ( A : INTEGER; B : BOOLEAN; C : BOOLEAN);
X end component ;
X
X signal S1 : INTEGER;
X signal S2 : BIT;
X signal S3 : CHARACTER;
X
X begin
X
X X : XIN port map
X ( A => S1'DELAYED( 1 ns ), B => S2'STABLE, C => S3'QUIET (0 ns));
X -- if the attributes were not signals an error would result
X
X-- end block;
Xend AB;
*-*-END-of-s-14-1-0-0016a.vhdl-*-*
echo x - s-14-2-0-0001a.vhdl
sed 's/^X//' >s-14-2-0-0001a.vhdl <<'*-*-END-of-s-14-2-0-0001a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-14-2-0-0001A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that identifiers declared in package STANDARD are not reserved words.
X-- DB 7/18/85
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
X
Xentity E is
Xend E;
X
Xarchitecture BB of E is
X-- L_X_1: block
X type BIT is (ZERO,ONE);
X type BOOLEAN is ('F','T');
X type CHARACTER is (EMPTY);
X type SEVERITY_LEVEL is (FORGET_IT);
X type INTEGER is range 0.0 to 9.9E9;
X type REAL is range 0 to 9E4;
X type TIME is (EARLY,ON_TIME,LATE,NEVER);
X signal TMIN : BIT;
X signal TMAX : BOOLEAN;
X begin
X process
X variable NATURAL : CHARACTER;
X variable POSITIVE : SEVERITY_LEVEL;
X variable STRING : INTEGER;
X variable BIT_VECTOR : REAL;
X variable XYZ : TIME;
X begin
X TMIN<= ZERO;
X TMAX <= 'F';
X NATURAL := EMPTY;
X POSITIVE := FORGET_IT;
X STRING := 9.1;
X BIT_VECTOR := 999;
X XYZ := NEVER;
X end process;
X-- end block;
X end BB;
*-*-END-of-s-14-2-0-0001a.vhdl-*-*
echo x - s-14-2-0-0002a.vhdl
sed 's/^X//' >s-14-2-0-0002a.vhdl <<'*-*-END-of-s-14-2-0-0002a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-14-2-0-0002A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that both predefined functions TMIN and TMAX return a value of type
X-- TIME predefined in package STANDARD.
X-- DB 7/18/85
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xuse P.all ;
Xpackage body P is
X function F1 (T1,T2:TIME) return BOOLEAN is
X variable XYZ : TIME;
X begin
X XYZ := TMIN(T1,T2);
X XYZ := TMAX(T1,T2);
X return TRUE;
X end F1;
Xend P ;
*-*-END-of-s-14-2-0-0002a.vhdl-*-*
exit
--
Steve Grout @ MCC VLSI CAD Program, Austin TX. [512] 343-0860
ARPA: grout@mcc.arpa
UUCP: {ihnp4,seismo,harvard,gatech,pyramid}!ut-sally!im4u!milano!grout