[comp.lsi] vhdl puzzle

smith1@uicbert.eecs.uic.edu (Ross Smith) (02/06/91)

Given the following architecture body.
D and E are converted to correct values, but F gives a 0.
Any ideas why this doesn't work (especially since it works elsewhere)?

architecure adder of adder is
 signal d,e,f : integer;
 begin
  process (add_enable, add_in1, add_in2)
    if (add_enable, = '1') then
      d <= bin_int2(add_in1); -- convert 32-bit bit array to integer 
      e <= bin_int3(add_in2); -- convert 40-bit bit array to integer 
      f <= (d + e); -- add the integers together
    end if;
  end process;
end adder;

aboulham@iro.umontreal.ca (02/07/91)

-------
> Given the following architecture body.
> D and E are converted to correct values, but F gives a 0.
> Any ideas why this doesn't work (especially since it works elsewhere)?

> architecure adder of adder is
>  signal d,e,f : integer;
>  begin
>   process (add_enable, add_in1, add_in2)
>     if (add_enable, = '1') then
>       d <= bin_int2(add_in1); -- convert 32-bit bit array to integer 
>       e <= bin_int3(add_in2); -- convert 40-bit bit array to integer 
>       f <= (d + e); -- add the integers together
>     end if;
>   end process;
> end adder;
----------
The problem here, is that f takes the present values of d and e (which
are either 0 or the left value of the integer type). The updated values of
d and e will be present on the next delta cycle. One possibility
is to add d and e to the sensititvity list of the process. You will
get the correct value on f some delta cycles later.



-------

carpent@SRC.Honeywell.COM (Todd Carpenter) (02/07/91)

-----------------------------------------------------------------------------
**Whirrr**  Net police!

  Hey, folks!  There is a VHDL newsgroup!  It is ideal for those nagging VHDL
  questions!  comp.lang.vhdl is the place to be!

-----------------------------------------------------------------------------

Ross> architecure adder of adder is

> [explanation of problem deleted, because someone already beat me to it as I
> was composing my response...]

You could get around this by declaring d and e variables within the scope of
the process, or by putting d and e in the process activation list, or by having
another process, or by making d,e,f assignments all concurrent, or by...

mjh@eng3.hep.uiuc.edu (michael j haney) (02/08/91)

carpent@SRC.Honeywell.COM (Todd Carpenter) writes:


>-----------------------------------------------------------------------------
>**Whirrr**  Net police!

>  Hey, folks!  There is a VHDL newsgroup!  It is ideal for those nagging VHDL
>  questions!  comp.lang.vhdl is the place to be!

>-----------------------------------------------------------------------------

Is there? Everytime I ask for comp.lang.vhdl on the machines at U of I,
I get: 

   Group comp.lang.vhdl not found

Has anyone actually *seen* comp.lang.vhdl?